If one IO bank is assigned to DDR3L controller whose logic level is SSTL-135 Class I, how the unused gpio can be used? what logic level should assigned to those gpio?
May I know how you're implementing the controller, is it soft or hard? As mentioned above, if it is hard, you may not be able to use other pins in that I/O bank as GPIO
It depends on the target device family and how you're implementing the controller: soft or hard? If it's hardened, like in newer devices, you may not even be able to use the other pins in the I/O bank as GPIO. What's your target device?
May I know how you're implementing the controller, is it soft or hard? As mentioned above, if it is hard, you may not be able to use other pins in that I/O bank as GPIO
