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XG_Kang
Novice
228 Views

how to use GPIOs in ddr3l bank

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If one IO bank is assigned to DDR3L controller whose logic level is SSTL-135 Class I, how the unused gpio can be used? what logic level should assigned to those gpio?

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ShafiqY_Intel
Employee
166 Views

Hi XG_Kang,

 

May I know how you're implementing the controller, is it soft or hard?
As mentioned above, if it is hard, you may not be able to use other pins in that I/O bank as GPIO

 

Regards,
Matt

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sstrell
Honored Contributor II
216 Views

It depends on the target device family and how you're implementing the controller: soft or hard?  If it's hardened, like in newer devices, you may not even be able to use the other pins in the I/O bank as GPIO.  What's your target device?

#iwork4intel

XG_Kang
Novice
206 Views

Arria 10 GX 270 

ShafiqY_Intel
Employee
167 Views

Hi XG_Kang,

 

May I know how you're implementing the controller, is it soft or hard?
As mentioned above, if it is hard, you may not be able to use other pins in that I/O bank as GPIO

 

Regards,
Matt

View solution in original post

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