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it spends me many days and nights ,any help will be appreciated!
i want to write data to fpga side sdram from hps,and my qsys system is do so
my code is
i have 3 questions
1:is to config the L3 register bit3 to 1 necessary? I find some document shows that i need to set the L3 register bit 3 to 1 to enable the h2f_axi_master
2.wheather the mm_bridge_1 ip is necessary in my design? i saw someone connnet the ddr3 ip-avl to h2f_axi_master immediately?
3.what is the possible reason for the bus error?
thx a lot!
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Hi,
I will be working on this case.
Please do allow some time to go through this case. I will reply ASAP.
Regards
Tiwari
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Thanks for your reply!
I have find out the reason of my “bus error”,it was because that I set the a wrong value of L3 register bit3.it should be 1 to enable the axi master,but i set it to 0 and the master was disabled.
However,i met another problem when i set correct L3 register.My code like this
any time i ran the code,it showed "write finished" and then was stuck.
i am a rookie on cyclonev and i have just learned this forweeks,i am sorry that my description may be unprofessional.if you can present me some easy examples of how to write data from hps to fpga ddr3 on cyclone v, it will help a lot.
thanks again for your answering my foolish problems
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Hi,
You can try below example on cyclone V. But this example is based on old version.
Let me know if you have any query on this.
Regards
Tiwari
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Hi,
I believe your enquiry has been answered. With that, I now transition this thread to community support.
Thank you.
Best Regards,
Tiwari
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
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