We are working on a solution that involves i2C communication between the FPGA and FX3 development kit and are experiencing problems reading data from the FPGA registers.
What we are trying to do is to read a single byte of data from a register (0x40) from the FPGA, using the FX3. The transaction should be as shown in the first image, where the FX3 does this steps:
The issue is that the FX3 does not release the Bus after sending the read address to the FPGA (step 7). This prevents the FPGA from sending the register data to the FX3 board. What could cause this problem?
I have attached a second image that shows the result we get on the signal analyzer
Thanks for your question. It appears to me that you are inquiring about Xilinx's FPGA. Can you please post this question in Xilinx forums instead? This community portal is reserved for Intel products including Intel FPGA (previously known as Altera FPGA).