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Altera_Forum
Honored Contributor I
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implementing serdes with altera cyclone iii develoment kit and texas EVM

hello i am using the altera cyclone III develoment board and connecting the ads5400 EVM(ADC) and DAC5682Z EVM to the HSMC port A and B repectively. 

 

to both are high speed converter therefore use lvds standard and i implement in FPGA serdes to work with less Fmax in FPGA. 

 

the cuestion is that the serdes implemented to the DAC work correctly but the serdes implemented to the ADC says: 

 

Error: Can't place pin "ADC[5]" with an I/O register at location Y2 that does not support I/O registers 

 

the problem is that the board enroute the bit 5 of data from the ADC to a clock pin into the FPGA(pin 96 of the HSM port LVDS clock in) and this pin don´t support I/O registers. 

 

for this reason, 

 

i can´t use serdes with this ADC EVM in cyclone III boards? 

 

there is any solution? 

 

thanks
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