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[User1580871742356367]

I'm trying on arria 10 SoC GHRD and like to add a register block on FPGA side to LW AXI4 interface for control and status. 

There is hps_lw_axi_master connected to SYS ID, PIO etc. 

How would my fpga register-block connected to this interface. Thanks. 

[sstrell]

Are you asking how to create a custom component and connect it to the lightweight bridge?  The Platform Designer user guide discusses this and this training goes into detail on the process:

https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys3000.html

#iwork4intel

[EBERLAZARE_I_Intel]

Hi,

Here are some useful guide and documentation on the LW bridge for your reference:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-device-design-guidelines.pdf#page=12

https://www.youtube.com/watch?v=RTmDgNXIwKQ

[User1580871742356367]

Hi, it's fine now. Thanks.