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max10 FPGA on chip flash write issue (without nios)


hi, can anyone help to answer this question?

I am trying to write data to max10 on chip flash(UFM) without using NIOS. what i am doing is to write a simple controller module and send the control signal required by on_chip_flash ip.

The steps can be described as follows:

1, disable write protection

2, do sector erase

3, write data to UFM

4, read back the data and verify the writing is successful or not.

5, enable write protection bit


 my question is if i read back signal after write, data is correct. However, if i disable the write process, and read the address

directly (same address as i write before), the data is always FFFF. It seems that the data is not write into flash successfully.

However, during the wite process, the statue signal from avmm_csr_readdata shows that the erase/write operation is successful. And the data can be read back correctly after the write process. Please help to solve this problem. Thanks!



Attached please find the cource code of the controller.




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Hi there,


I was wondering if you ever got a reply from Altera/Intel on this. I'm having a similar problem. I'm using Quartus 18.0 and I've created an internal flash controller IP block. I can read the Control and Status registers correctly, but whenever I read from the flash using the Data avalon interface it seems to be ignoring the requested address. It just seems to increment automatically between addresses, but takes no account of the address I actually request.


Did you manage to solver your issue?



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