newbee: PCI-e Dev Kit Help

[Altera_Forum]

Hello, 

 I am very new to the FPGA world and trying to get my head around a lot of new things, So please forgive me if my question seems very basic or confusing. Please feel free to ask for clarification   I just started working with a PCI-e dev kit that among other includes a stratix II gx fpga. I need to use the fpga to talk to an app over the pci bus. From what I understand altera provides a an PCIe IP megacore that makes this very easy, but they want $16000 for it. Researching the forums I found people are using an openCore for PCI. All this is getting a little confusing.  1.)My first question is that what si the difference between megacore and opencore 2.)Second question is that if it is possible to implement this without the IP megacore 3.) Last is that is there any tuotrial, reading material that can help me understant this.    Any help will be appreciated.

[Altera_Forum]

1) Megacore: IP developed by Altera to run on their FPGAs. This can be anything for a simple added to the PCI-Express Core.opencores (http://www.opencores.org) is a website that provides open source IP, and a good resource.  

 2) What are you trying to implement? If you mean a PCIe endpoint than yes it is possible to implement it without using a megacore. Other companies provide a PCIe endpoint that can be implemented in the Stratix II GX.  3) I suggest you goto the demonstration center (http://www.altera.com/education/demonstrations/dem-index.html) on Altera's website. There are many online demonstrations that will help bring you up to speed with Altera's Software and FPGA concepts.

[Altera_Forum]

Hi rmorley, 

 Thanks for your reply. I actually did check out opencores website after I my post here. You are right, the site is a good resource.   I am actually trying to use the stratix II GX as the go between my pc application and another peice of external hardware. I get info from the hardware that I pass on to the pc application over the PCIe and that app passes me information (video) based on what I give it. This FPGA has specific pins to deal with PCIe but I am not sure I will implement the whole timing/interrupt issues. I am not sure how easy the pci megacore will make it to implement.

[Altera_Forum]

Altera tries to make thier megacores as straight forward as possible. When you are talking about the timing/interrupt issue, do you mean from the API's point of view or for the hardware level? If it is from the hardware level the PCI-Express Core Manual for the megacore will explain how to set up the timing and how to send interrupts.