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Altera_Forum
Honored Contributor I
791 Views

nios 2 dosen't work on Stratix II GX PCIE development board

Hi, all, 

 

I'm new here and have a problem. 

 

I tried to run nios 2 on my stratix II GX PCIE development board. I followed the Nios 2 hardware tutorial step by step. The project compiled and the sof file was downloaded to the FPGA successfully. But when I tried to run a hello world or a count binary project on the nios2 system. The following message showed: 

Using cable "USB-Blaster [USB-0]", device 2, instance 0x00 

Pausing target processor: not responding. 

Resetting and trying again: FAILED 

Leaving target processor paused 

 

I searched and tried all the possible solutions online, but just couldn't figure out how to solve it. I tried the same design on a DE2 board and it worked fine. But with this stratix ii gx pcie board, I don't know... Following are some information of my project. 

 

Quartus II version: 9.1 full featured 

Nios II: 9.1 

clock pin: I set to 100MHz oscillator(Pin_A20) 

 

If anyone could give me some suggestions, I'd really appreciate it! 

 

Thanks, 

Xiaorong
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5 Replies
Altera_Forum
Honored Contributor I
69 Views

You could check if the clock is sent properly to the FPGA, on the correct pin and at the correct frequency. 

Check also the polarity of all the reset signals. 

Are you using a PLL? In that case what is the status of the "locked" output?
Altera_Forum
Honored Contributor I
69 Views

Daixiwen, 

 

Thanks for your suggestion. I'll try it. I'm not using a PLL. Since the system is very simple, just including a cpu, an on-chip memory, a JTAG UART and a system clock timer, I just use the 100 MHz external clock to drive all the components. The reset signal is set to Vcc. Actually I just assigned one pin, the clock.  

 

Every time I tried to download the sof file to the FPGA, there was a message saying "expect 1 device, but detect 2. Operation failed". I could only press the auto-detect button, and then 2 devices showed up, a MAX II CPLD and a stratix ii gx fpga. Then I downloaded the sof file to the fpga with no error. I'm not sure if this is a problem. 

 

Thanks, 

Xiaorong
Altera_Forum
Honored Contributor I
69 Views

Hi Daxiwen, 

 

Could you please tell me how to check if the clock is properly sent to the FPGA?... Can we measure the frequency of one pin in the FPGA chip? Thank you.
Altera_Forum
Honored Contributor I
69 Views

I found the problem. It was the IO standard of the clock pin. It should be set to LVDS.

Altera_Forum
Honored Contributor I
69 Views

Just to answer your question, you can use a scope to see if the clock signal is getting to the FPGA, but in my opinion the best way to check if it is acquired correctly by the FPGA is either Signaltap (if you have an unrelated clock somewhere) or even better to connect it to a pll and check it's "locked" output.

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