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niosii ethernet std design 3c25 neek critical warnings

Altera_Forum
Honored Contributor II
925 Views

Hi, 

 

When I build the NIOS2 Ethernet Standard Design for the 3C25 Neek I see some critical warnings (see below), and I was curious if there are any patches available for this issue, or perhaps there is someplace I can obtain the missing 'sdram_phy_ddr_timing.sdc' file? 

 

Also, when I write, and then read back, the SGDMA control registers using the base address in the generated file 'system.h', I don't appear to successfully modify this register. Closer examination reveals that the macro ETHERNET_SUBSYSTEM_SGDMA_TX_BASE specifies a base address of 0x800a440. In QSYS I see that the "ethernet_subsystem.ethernet_bridge" is at 0x800a000-0x800a7ff and that in the ethernet subsystem "sgdma_tx.csr" is at 0x440-47f. So that probably indicates that QSYS is reporting also the same base address, and therefore I am pretty clueless as to why the register isn't responding in code and also when manipu;lating it in gdb. I do use code like this for accessing the memory mapped registers bypassing the cache (which does work for example with the Altera TSE registers). 

 

static inline uint32_t ioRead32 ( const uint32_t * const pSrc ) 

return __builtin_ldwio ( ( void * ) pSrc ); 

 

static inline void ioWrite32 ( uint32_t * const pDest, const uint32_t newVal ) 

__builtin_stwio ( pDest, newVal ); 

 

 

Critical Warning: No exact pin location assignment(s) for 1 pins of 113 total pins 

Info: Pin flash_a[0] not assigned to an exact location on the device 

Critical Warning: Synopsys Design Constraints File file not found: 'sdram_phy_ddr_timing.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. 

Critical Warning: Synopsys Design Constraints File file not found: 'sdram_phy_ddr_timing.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. 

Critical Warning: Timing requirements not met 

Critical Warning: Timing requirements not met 

Critical Warning: Timing requirements not met
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7 Replies
Altera_Forum
Honored Contributor II
163 Views

PS I am using Quartus II version 11.0 SP1

Altera_Forum
Honored Contributor II
163 Views

I notice that this file does exist in the Ethernet standard design 

 

niosii-ethernet-standard-3c25/eth_std_main_system/synthesis/submodules/eth_std_main_system_sdram_phy_ddr_timing.sdc
Altera_Forum
Honored Contributor II
163 Views

and I see this at line 288 of niosii_ethernet_standard_3c25.qsf 

 

set_global_assignment-name SDC_FILE sdram_phy_ddr_timing.sdc
Altera_Forum
Honored Contributor II
163 Views

hm ... I notice that the quartus settings dialog has a line like this 

 

eth_std_main_system/submodules/eth_std_main_system_sdram_phy_ddr_timing.sdc 

 

and also a line like this 

 

sdram_phy_ddr_timing.sdc 

 

so maybe this second line is superfluous?
Altera_Forum
Honored Contributor II
163 Views

I figured out the sgdma ctrl register write/readback issue. I reread the Altera doc carefully, and the offsets for stat, ctrl, nxt are 0, 4, and 8 respectively. These offsets look by coincidence like byte offsets for sequential, contiguous 32 bit words, but in fact they are actually 32 bit word offsets. The doc is actually correct, and I need to read more carefully in the future.

Altera_Forum
Honored Contributor II
163 Views

Still stuck attempting to resolve this error (which prevents timing from being made).  

 

Critical Warning: Synopsys Design Constraints File file not found: 'sdram_phy_ddr_timing.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. 

 

I am using the ethernet standard design unmodified. The file in question does exist under a different name - eth_std_main_system_sdram_phy_ddr_timing.sdc. 

 

When I search the entire design I find only this in a hif file. This file _does_ exist so I don't know how to proceed. 

 

lib_eth_std_main_system 

eth_std_main_system|synthesis|submodules|eth_std_main_system_sdram_phy_ddr_timing.sdc 

lib_eth_std_main_system
Altera_Forum
Honored Contributor II
163 Views

installing Quartus 11.1 sp2 appears to resolve this issue

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