FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5922 Discussions

node is missing source error when using Avalon Memory-Mapped Master Templates

Altera_Forum
Honored Contributor II
1,119 Views

Hello, 

I am trying to connect my custom component to the SDRAM so I downloaded the Avalon MM master template from: 

http://www.altera.com/support/examples/nios2/exm-avalon-mm.html 

I used the burst read master template and added SDRAM controller from SOPC builder and called this component avalon then created a quartus project with a simple verilog file user_logic.v that contains my logic to write a word to the SDRAM and finally connected those components together but when I compile I get those errors: 

 

 

Error: Node "avalon:a|burst_read_master_0:the_burst_read_master_0|burst_read_master:burst_read_master_0|coe_control_fixed_location_d1" is missing source 

 

Error: Node "avalon:a|burst_read_master_0:the_burst_read_master_0|burst_read_master:burst_read_master_0|reads_pending[0]" is missing source 

Error: Node "avalon:a|burst_read_master_0:the_burst_read_master_0|burst_read_master:burst_read_master_0|reads_pending[4]" is missing source 

Error: Node "avalon:a|burst_read_master_0:the_burst_read_master_0|burst_read_master:burst_read_master_0|reads_pending[3]" is missing source 

Error: Node "avalon:a|burst_read_master_0:the_burst_read_master_0|burst_read_master:burst_read_master_0|reads_pending[2]" is missing source 

Error: Node "avalon:a|burst_read_master_0:the_burst_read_master_0|burst_read_master:burst_read_master_0|reads_pending[1]" is missing source 

 

It's my first time to use this template, Am I using right ? 

The connection diagram is attached.
0 Kudos
0 Replies
Reply