Dear Intel Support/Expert
I have a simple question, for AN708, it is focused on FPGA side development. it provides driver and a demo application software. in my case, if I want to add a group of resisters to the Bar4 memory space. how to leverage the intel provided software to access it?
I searched intel website,
and some of the links provided in the page were broken.
could you please provide a new link?
Can you specify which link you are looking at ? So that I can provide the new link for you.
For BAR size configuration, I suggest you to refer to
It might not be exact what you looking at as that is AVMM design example. Hope this help.
I roughly know how to reconfigure the BAR on the FPGA side. I want to know how to test it on Host PC, for example the Boardtestsystem.exe software. The BAR is predefined by the example FPGA project, if I understand correctly, after I update the BAR content with my application, is there any example/ tutorial to create/update the boardtestsystem.exe software so I can access all memory/register space to test the new FPGA.
now I have a new FPGA on the dev kit board, I need to test it with a customized BTS, I want to know is there any document from Intel to instruct developers to create BTS.
could you please help find out the following links.
it may be what I am looking for.
Here is updated GUI: http://www.alterawiki.com/uploads/e/e7/GUI_for_AN431.zip
This GUI can be used with Cyclone-V GT example, as well as all previous PCIe examples.
Simple version of software source code: http://www.alterawiki.com/uploads/b/b4/Alt_pcie_qsys_simple_sw.zip
Document of the software : http://www.alterawiki.com/uploads/7/74/Simple_PCIe_soft_readme.doc
in another words, I am looking for a tutorial to develop the software in this zip package.
64-bit Windows driver and application:File:Gui package 090 80000000.zip.
In the package, there is a word document which explains how to install the driver, what additional software needed to be installed, and how to run the application.
Please refer to https://cdrdv2-public.intel.com/653681/an431.pdf
For the qsys design,
Please refer to https://www.youtube.com/watch?v=d43Pqc_IZpg&ab_channel=IntelFPGA
There is step by step video there for better understanding.
For the last link, I don't find it in any place, it might be obsolete.
Will submit an internal ticket for the link-broken issue
For other PCIe design, you may get it at
Hope this clarified, Regards,
Happy new year to you.
I wish to follow up with you about this Forum case.
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Else I would like to have your permission to close this forum ticket
We have not hear from you and this Case is idling. It is not recommended to idle for too long.
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