hi. I am trying to write a simple VHDL code to write some data to the ssram on the DE4 board and read it back.it is not optimized at all but serves the purpose. the project is running at 30MHZ and below very well but when I try higher freq. it fails. second clock from pll is 180 degree shifted from first. any suggestion or hint is very appreciated. thank you very much
First of all consider your ssram timing specifications: you may need to add more waitstates (especially on reads) when you increase clock frequency.Remark: I see that in your code you never deassert read and write signals, except on reset; this probably doesn't matter for your current purposes, but it's not correct.
Hi Cris72.Thanks for your attention and reply. About the read and write signals, they are driven from the topModule for just 1 clock for each read or write access. And I have seen the datasheet of ssram. it is pipelined 1M*16bit from ISSI. there is nothing stated about the extra wait states. It is very odd but extra wait states worked when using higher frequency's while there is nothing about it in the datasheet ! Thanks for your time.