I have a minimal Verilog program which I using successfully to program the Arria V FPGA on the dev kit. I light a few LEDs with the switches, nothing more. Now I want to program the flash device on the dev kit, so it programs auto-magically when the power is turned on.After a few hours of frustration, I finally found a link that told me I had to open the Programmer as an admin to do what I want. After this, I was able to 'attach flash device', and selected 1GB, which is what is written in the schematic for this dev board. I used the edit - convert programming files function to create a .pof file from my .sof file. Indications are that the .pof was created successfully. I then use the change file utility to attach the .pof file to the 1GB CFI device. All looks good so far. Just one note, in the programmer window, in the file column, where it lists my .pof file, under that there is a line that says 'PAGE 0' and another line which says 'OPTION BITS'. When I select the check box to program/configure the .pof file, it automatically checks the same boxes for the 'PAGE 0' and 'OPTION BITS' lines. I assume that is what it should be doing. Now the problem, when I hit the 'start' button to begin the device programming, it gets to 88%, then gives me the following errors; 209062 Flash Loader IP not loaded on device 1 209053 Unexpected error in JTAG server -- error code 5 209012 operation failed Can anybody tell me what I'm doing wrong? Do I need to use something other than JTAG to configure the CFI device?
Hi,Did you check the Arria V start kit user guide on the steps to program the CFI flash. Typically the user guide contains all the instruction for the flash programming. If you want to program the .pof into the CFI flash then you need to implement the PFL IP into the MAX V/MAX II device on the boards to access the CFI flash. You can check the PFL IP user guide for the details. Anyway before that it better to check the Arria V start kit user guide on the steps to program the CFI flash.