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qsys-generate is taking a very long time to generate updates

I am using two versions of qsys-generate to build files. The first one generates the board file, but the one that generates the verilog is taking a very very very long time. I mean 1-2 hours. Is that typical? Is there a way to improve performance of qys-generate?

 

Here is the script I'm using

#!/bin/bash   qsys_file=$1 filename=${qsys_file%.*}   #qsys-generate system.qsys --block-symbol-file --output-directory=acl_iface_system --family="Cyclone V" --part=5CSEBA6U23I7 time qsys-generate ${qsys_file} --block-symbol-file --output-directory=${filename} --family="Cyclone V" --part=5CSEBA6U23I7 time qsys-generate ${qsys_file} --synthesis=VERILOG --output-directory=${filename}/synthesis --family="Cyclone V" --part=5CSEBA6U23I7

 

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I haven't experienced this before. Could you help to share your qsys files?

For debugging purposes, may I suggest to:

1) Install the latest Quartus version and regenerate the qsys file.

2) Use a different machine and check is there any improvement

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The customer able to find the root cause and it was due to the type of file system used on the customer's virtual machine.

Using mounted block disk instead of the mounted disk from the host operating system helps to improve the time.

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