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questions about Cyclone V SOC dev kit HPS DDR3 DQ pins

Honored Contributor II

Hello everyone,  


I have a question about the Cyclone V SOC dev kit schematic. On page 14 of C5_SOC_DEVKIT_D2.pdf, DQ pins of DDR3 seem all scrambled, like DQ0 of DDR3 is connected to HPS_DDR3_DQ2, DQ1 of DDR3 is connected to HPS_DDR3_DQ4. Is it supposed to be that way or it is just errors on the schematic? Could anybody here help me out please? 


Thanks a lot!! 


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Honored Contributor II


Good question. I had to think about it for a bit until I realized that for data pins on a memory, the order doesn't matter. This is because you should read back the bits in the same order you wrote them, for a particular address. Hopefully that makes sense. So, they look scrambled but the choices were probably made to ease routing. Since the data bit ordering doesn't matter, choose what makes PCB trace routing the easiest for you. Make sense?
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