I don't know why, adding from the library a 1-port RAM makes the following vhdl crash, it' s a dummy code just to reproduce the error (which is:Error(17729): VHDL error at float_generic_pkg_vhdl2008.vhd(72): formal generic package fixed_pkg does not match with actual"). Commenting out use IEEE.float_pkg.all; compiles, so I wonder why that simple RAM and the float package have a problem (on Quartus Prime pro, latest version)
-- VHDL Code for OR gate
-- Entity declaration
entity trial is
port(A : in std_logic; -- OR gate input
B : in std_logic; -- OR gate input
Y : out std_logic); -- OR gate output
-- Dataflow Modelling Style
-- Architecture definition
architecture orLogic of trial is
--signal P: float64;
Y <= A OR B;
I had no problem at synthesizing the posted code on my end. No error appears. Check file attached. (Quartus Pro 22.2, VHDL2008)
I found this link https://stackoverflow.com/questions/73903583/formal-generic-package-fixed-pkg-does-not-match-with-actual-float may be try restarting the project from scratch or deleting qdb recompile.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.