FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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schematics and layout guidelines for the eval kit of the EC2630QI

Honored Contributor II

Im looking for the schematics for evb-ec2630qi (http://www.mouser.com/productdetail/enpirion/evb-ec2630qi/?qs=sgaepimzzmvcrsgomffep6905dcuu8ltd0wpwr...) (Eval kit for the EC2630QI). I am hoping that there is footprint recommendation for this part too. It seems like EN5311QI, EN6347QI and EN23F2QI all have footprint recommendations and even a sample schematic but the EC2630QI doesn't. For instance the M/S only says" Master/Slave pin for clock synchronization. Logic low = Master.Logic high = Slave" in the description but it fails to provide the definition of Logic High and Low. Even the simplified circuit on Page 1 doesnt show the M/S connection. Please assist.

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Honored Contributor II

If you check out the data sheet here (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ds/ec2630qi_05996.pdf) , and look on page 12, you should see the recommended footprint.