FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5892 Discussions

simple frame buffer to vga on DE1-SOC

Altera_Forum
Honored Contributor II
2,272 Views

Hi guys, 

 

I'm a bit of a novice to qsys and the De1-soc so i was wondering if someone could help me. I'm interesting in reading data from an sd card and using a frame buffer to view it on the vga output of the cyclone V de1-soc. Is there anyone here who can provide a sample qsys design of how this is supposed to look like? Id image it would pretty quick for someone experienced with qsys to set this up. 

 

Thanks a lot for any help!
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
997 Views

You may check into the following reference design link at Altera web to see if can find any similar design that suit your requirement: 

https://www.altera.com/products/reference-designs/all-reference-designs.html
0 Kudos
Altera_Forum
Honored Contributor II
997 Views

Ok thank you but I didn't seem to find anything on the link provided :(

0 Kudos
Altera_Forum
Honored Contributor II
997 Views

Several of the Terasic demo board CDs have demos for VGA. I don't know about the DE1-SOC, but some of the other DE series boards have VGA demos. You will need to use a processor either with linux or without to operate the SD card. You have an ARM already on the SOC, it would work. Start with the GHRD for the DE1-SOC and add your VGA frame buffer to it.

0 Kudos
Altera_Forum
Honored Contributor II
997 Views

Dear all, 

 

I want to manually start VGA output using Frame Reader and Clocked Video Output. 

 

As a reference I'm using project form SystemCD: DE1-SoC_v.3.1.1_SystemCD\Demonstrations\SOC_FPGA\DE1_SOC_Linux_FB. (so there is no need to attach  

The original design is working correctly with DE1_SoC_FB (displaying console) 

Then I change SD card image to DE1_SoC_SD (simple OS without any video) and try to configure FrameReader manually: 

 

 

# include <stdio.h> # include <unistd.h> # include <fcntl.h> # include <sys/mman.h> # include "hwlib.h" # include "socal/socal.h" # include "socal/hps.h" # include "socal/alt_gpio.h" # include "hps_0.h" # include "frame_reader.h" # define REG_BASE 0xFF200000 # define REG_SPAN 0x00200000 void* virtual_base; void* video_addr; void* led_addr; void* sw_addr; int fd; int switches; int i,j; uint8_t video_ram; int main(){ fd = open("/dev/mem", (O_RDWR|O_SYNC)); virtual_base = mmap(NULL, REG_SPAN, (PROT_READ|PROT_WRITE), MAP_SHARED, fd, REG_BASE); led_addr = virtual_base + LED_PIO_BASE; sw_addr=virtual_base + DIPSW_PIO_BASE; video_addr = virtual_base + ALT_VIP_VFR_VGA_BASE; *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_FRAME_0_BASE_ADDR) = (uint32_t)video_ram; usleep(100); *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_FRAME_0_WORDS) = 1024*768*4*8/128;//p. 13-1/2 - pixels*planes*bits_per_pixel_per_plane/master bus width *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_FRAME_0_SINGLE_CYCLE_CPATERNS) = 1024*768;//p. 13-1 - color planes = number of pixels *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_FRAME_0_WIDTH) = 1024; *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_FRAME_0_HEIGHT) = 768; *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_FRAME_0_INTERLACED) = 3; *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_FRAME_SELECT) = ALTERA_FRAME_READER_FRAME_SELECT_0; *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_CONTROL) = ALTERA_FRAME_READER_CONTROL_GO; for(i=0;i<1024;i++){ for(j=0;j<768;j++){ video_ram=i+j; } } /*while(1){ *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_CONTROL) = ALTERA_FRAME_READER_CONTROL_GO; *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_CONTROL) = 0; }*/ while(1){ switches=*(uint32_t *)sw_addr; *(uint32_t *)led_addr=switches; usleep(1000000); printf("%u %zu %zu\n", switches, *((uint32_t *)(video_addr)+ALTERA_FRAME_READER_FRAME_0_BASE_ADDR), (uint32_t)video_ram); } return 0; }  

 

# ifndef _ALTERA_FRAME_READER_H # define _ALTERA_FRAME_READER_H //#define ALTERA_FRAME_READER_ 0x # define ALTERA_FRAME_READER_CONTROL 0x0 # define ALTERA_FRAME_READER_CONTROL_GO 0x1 # define ALTERA_FRAME_READER_CONTROL_INT_EN 0x2 # define ALTERA_FRAME_READER_STATUS 0x4 # define ALTERA_FRAME_READER_STATUS_STATUS 0x1 # define ALTERA_FRAME_READER_INTERRUPT 0x8 # define ALTERA_FRAME_READER_INTERRUPT_RESET 0x1 # define ALTERA_FRAME_READER_FRAME_SELECT 0xC # define ALTERA_FRAME_READER_FRAME_SELECT_0 0x0 # define ALTERA_FRAME_READER_FRAME_SELECT_1 0x1 # define ALTERA_FRAME_READER_FRAME_0_BASE_ADDR 0x10 # define ALTERA_FRAME_READER_FRAME_0_WORDS 0x14 # define ALTERA_FRAME_READER_FRAME_0_SINGLE_CYCLE_CPATERNS 0x18 # define ALTERA_FRAME_READER_FRAME_0_RESERVED 0x1C # define ALTERA_FRAME_READER_FRAME_0_WIDTH 0x20 # define ALTERA_FRAME_READER_FRAME_0_HEIGHT 0x24 # define ALTERA_FRAME_READER_FRAME_0_INTERLACED 0x28 # define ALTERA_FRAME_READER_FRAME_1_BASE_ADDR 0x2C # define ALTERA_FRAME_READER_FRAME_1_WORDS 0x30 # define ALTERA_FRAME_READER_FRAME_1_SINGLE_CYCLE_CPATERNS 0x34 # define ALTERA_FRAME_READER_FRAME_1_RESERVED 0x38 # define ALTERA_FRAME_READER_FRAME_1_WIDTH 0x3C # define ALTERA_FRAME_READER_FRAME_1_HEIGHT 0x40 # define ALTERA_FRAME_READER_FRAME_1_INTERLACED 0x44 # endif /* _ALTERA_FRAME_READER_H */  

 

But VGA screen shows "No Signal". I modified the code in different ways, according to several therads on this forum, but nothing helped - changing interlacing, words, single cycle patterns etc. 

 

Also nowhere i found complete QSys design with working code - sometimes there is a design but without working simple code, sometimes code reported to work, but without details of the design. 

 

Thank you in advise for any help.
0 Kudos
Reply