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simple socket server is simple, but still need help

Altera_Forum
Honored Contributor II
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Hi all, 

 

Thanks for reading this thread, hope you could help me out. 

 

My situation is here: 

 

hardware: cIII 120 develop board 

software: QII 9.1 sp2, Nios II 9.1 sp2 

 

What i have done: 

1. copy the C:\altera\91\nios2eds\examples\verilog\niosII_cycloneIII_3c120\triple_speed_ethernet_design to my project fold and open with QII 

2. open sopc builder and run generate 

3. back to QII and compile to generate sof (time limited version) 

4. open nios eclipse ide, create a new project with simple socket server template 

5. to avoid troulbe, modife get_mac_addr() as: 

****************************************** 

int get_mac_addr(NET net, unsigned char mac_addr[6]) 

mac_addr[0]='0'; 

mac_addr[1]='0'; 

mac_addr[2]='0'; 

mac_addr[3]='0'; 

mac_addr[4]='0'; 

mac_addr[5]='0'; 

return 0; 

// return (get_board_mac_addr(mac_addr)); 

****************************************** 

6. run app as "Nios II hardware" 

 

what I got: 

 

=============== Software License Reminder ================ 

This software project uses an unlicensed version of the NicheStack TCP/IP 

Network Stack - Nios II Edition. If you want to ship resulting object 

code in your product, you must purchase a license for this software from 

Altera. For information go to: "http://www.altera.com/nichestack

===================================================== 

InterNiche Portable TCP/IP, v3.1  

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  

prep_tse_mac 0 

Static IP Address is 192.168.1.234 

prepped 1 interface, initializing... 

[tse_mac_init] 

INFO : TSE MAC 0 found at address 0x08004000 

INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0] 

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] 

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... 

INFO : PHY[0.0] - Auto-Negotiation PASSED 

INFO : PHY[0.0] - Checking link... 

INFO : PHY[0.0] - Link established 

INFO : PHY[0.0] - Speed = 100, Duplex = Full 

OK, x=1, CMD_CONFIG=0x00000000 

MAC post-initialization: CMD_CONFIG=0x04000203 

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created 

mctest init called 

IP address of et1 : 192.168.1.234 

Created "Inet main" task (Prio: 2) 

Created "clock tick" task (Prio: 3) 

Simple Socket Server starting up 

[sss_task] Simple Socket Server listening on port 30 

Created "simple socket server" task (Prio: 4) 

 

 

Everything looks smooth, but I cannot ping, telnet or whatever else. 

When I ping, the RX light is flashing, but TX light not. 

 

So, if you know something about this, please reply. 

 

Thank you.
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4 Replies
Altera_Forum
Honored Contributor II
365 Views

Yeah I don't know if a MAC address of 00:00:00:00:00:00 is going to work. You might start there. 

 

Jake
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Altera_Forum
Honored Contributor II
365 Views

Hi Jake, 

 

Thank you for reply. 

I did try this 

 

************************************************** 

to avoid troulbe, modife get_mac_addr() as: 

****************************************** 

int get_mac_addr(NET net, unsigned char mac_addr[6]) 

mac_addr[0]=0xB7; 

mac_addr[1]=0xA7; 

mac_addr[2]=0xED; 

mac_addr[3]=0xFF; 

mac_addr[4]=0xFF; 

mac_addr[5]=0xFF; 

return 0; 

// return (get_board_mac_addr(mac_addr)); 

****************************************** 

************************************************** 

it fails too.  

 

waiting for help
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Altera_Forum
Honored Contributor II
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more info: 

I disable DHCP in wizard and I use cross cable to connect board and PC directly. 

 

is this a rare problem? 

nobody can help?
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Altera_Forum
Honored Contributor II
365 Views

Have you built your project successfully? I got errors when buiding as I use the SSS example on cyclone II

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