FPGA, SoC, And CPLD Boards And Kits
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termination of jtag signals

Altera_Forum
Honored Contributor II
‎05-28-2010 02:40 PM
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I am developing a development board for CPLD EPM7064S and will be using parallel cable to program the chip.As in byteblaster schematic,i have to use 74HC244 as level translator after 23 pin header so that it gives me 10 pin connection containing 4 jtag signal TCK,TMS,TDO and TDI. 

 

The confusion is about connecting these to CPLD.In some designs people have terminated all four using pull up resistors of 1k or 47k.....others have pulled up the three and pulled down the TCK....why is it so? what should i do as i have not studied standard jtag implementation. 

 

Kindly help
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Altera_Forum
Honored Contributor II
‎05-28-2010 05:05 PM
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Altera documentations (e.g.configuration handbook) is very clear in this respect. You should have a pull-down for TCK and pull-ups for the other signals.

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