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the tx_serial_clock and tx_load_enable signal of one exteral can not drive the lvds_tx in different BANK of Arria V?

Lambert
New Contributor I
366 Views

Hello everyone,

I have one problem is that I need several LVDS pairs for high-speed data output, I only can select the lvds pairs in diffent bank because of layout restrictions. I chose the output of one external PLL to drive them, but it always was fittered failure, I read the clock , PLL and I/0 part of Arria V datasheet, it can't say that the same external PLL can not drive lvds pairs in different BANK obviously. I want to know what kind of routing resources (GCLK, RCLK or PCLK) the arriav_pll_lvds_output of the PLL chooses. altera_pll_output.GIF

Can you give me some help?

Thank,

Lambert

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8 Replies
SreekumarR_G_Intel
156 Views

Hello Lambart,

Answer to your questions is it depends , i wont be able to provide the high level answer here like yes or no. Instead would it possible to share the design ? I will check your LVDS bank mapping and will help me to come to an conclusion .

 

Thank you ,

 

Regards,

Sree

Lambert
New Contributor I
156 Views

Hi Sree,

I can provide part:

arriav_pll_lvds_output #(.pll_loaden_enable_disable("true"), .pll_lvdsclk_enable_disable("true")) arriav_pll_inst( .ccout({load_en_i,clk_i), .loaden(load_en), .lvds_clk(clk));

altlvds_tx altlvds_tx_u0(.tx_enable(load_en), .tx_in(data), .tx_inclock(clk), .tx_out(dat_out));

 

I instances several lvds_tx IP, and assignment them to different lvds channel in three bank, like below:

(AF28,AG28), (AK26,AK25),(AE27,AE26) (3A BANK)

(F10,E10) (7B BANK)

(H6,G6),(H7,G7) (7A BANK)

My fpga is Arria V 5AGXBA3DF31.

Best regards,

Lambert

SreekumarR_G_Intel
156 Views

Hey Lambart ,

sorry , I came back from vacation :) ..if you dont mind Can i get the qar file? which make my life easy :)

 

Thank you ,

 

Regards,

Sree

Lambert
New Contributor I
156 Views

Hi Sree,

My code is under internal network, and I can not download it, and I don't have the quartus II software on Windows System, so I am sorry to that I can not support the .qar file.

Best regards,

Lambert​

SreekumarR_G_Intel
156 Views

Hello Lambert,

No problem , I re-created the issue you were seeing. Here is my thought on the same .

i) I am able to FIT differnet bank in the same row (i.e 3A ,4A ,4B,4C & 4D) with PLL.

ii) Quartus wont be able to route PLL between Bank 3A to 7A. from the Archteuture of Arria V A3 device it is clear that it is not possible directly.

One idea ,

We can try to use the PLL cascade and see you able route from 3A bank to 7A . I didn tried as of now .

 

Attavhed file for your reference for differnet bank in bottom LVDS channel.

 

Thank you ,

 

Regards,

Sree

Lambert
New Contributor I
156 Views

Hi Sree,

Thanks for your help, I have one problem that if I use the PLL cascade method to provide clock for lvds output locating in 3A and 7A , that means I will need two PLL output clk to drive different lvds output , if so, can I get the better phase relationship between the lvds output locating in 3A bank and the lvds output locating in 7A bank? Because I design this project for 16-bit DAC chip, so the lvds output needs good phase relationgship between each other.

 

Best regards,

Lambert

SreekumarR_G_Intel
156 Views

Hello Lambert,

There will be option in PLL to compenstate the phase or you can use the source syn options too.I cant give the definitive number but it is good to try the options

 

Thank you,

 

Regards,

Sree

 

Lambert
New Contributor I
156 Views

Hi Sree,

Thanks for your help.

Best regards,

Lambert

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