FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5930 Discussions

the tx_serial_clock and tx_load_enable signal of one exteral can not drive the lvds_tx in different BANK of Arria V?

Lambert
New Contributor I
‎11-25-2019 08:23 AM
345 Views

altera_pll_output.GIFHello everyone,

 

 I have one problem is that I need several LVDS pairs for high-speed data output, I only can select the lvds pairs in diffent bank because of layout restrictions. I chose the output of one external PLL to drive them, but it always was fittered failure, I read the clock , PLL and I/0 part of Arria V datasheet, it can't say that the same external PLL can not drive lvds pairs in different BANK obviously. I want to know what kind of routing resources (GCLK, RCLK or PCLK) the arriav_pll_lvds_output of the PLL chooses. 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 Can you give me some help?

Thank,

Lambert

0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.