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Valued Contributor III
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transceiver design examples

Hi, 

 

I would like to modify a design example named aii_4ch_10b_2000Mbps (transceiver design example) in order to use CMU PLL0 for first two channels and CMU PLL1 for the other two.  

I have a couple of problems (Quartus 10.1 sp1): 

 

1) the XCVR component doesn't provide any configuration to select a given CMU PLL.  

2) should I use an XCVR reconfig? Why neither XCVR nor the the XCVR reconfig are available in the left tree list of Qsys or SOPC builder? 

3) I tried to overcome the problem using the Megawizard and discovered that the "Custom PHY 10.1" cannot be instantiated. It is simply greyed out. 

 

Thx, 

Antonio.
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Valued Contributor III

Re: transceiver design examples

If you go to <altera install dir>/ip/altera, there is a file called altera_components.ipx which manages all the metadata for your component library. I figured that if you change the "internal component" property of the component you need from TRUE to FALSE, then it will appear in the QSYS or SOPC tree on the left. However, I don't know whether the generated the component instance will work. They must be hidden for a reason! 

 

I have a similar problem with the 10G PHY components, Altera provides reference designs for custom-PHY or low latency-PHY, however, none of the components are available from the left side component tree in QSYS. why is that?? Should they be available??
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Valued Contributor III

Re: transceiver design examples

I enabled the Custom PHY Transceiver doing as you suggested. 

I didn't expect that a tool like Quartus could have such problems. 

Furthemore, with Qsys I cannot select CMU PLL0/1 for a given channel and it is not clear which relation there should be between input reference clock and Data Rate.
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