unable to create symbol file for current file (Verilog HDL file) in Quartus prime pro 20.3

[Parisa]

Hi everyone,

I am working on Quartus prime pro 20.3 and I was going through "my first fpga tutorial". Here it says after creating simple_counter.v verilog code, we need to go to create/update and create block diagram for current file. 

My whole create/update file is disabled and I even in disable mode, I dont even have the option to create block diagram for current verilog file

can anyone help me?

Thank you

[SyafieqS]

Hi Parisa,

This this option has been removed from the Intel® Quartus® Prime Pro Edition software starting version 18.0 and only available in Standard Edition. The reason is because symbol files are not an industry standard format. Below is KDB related to your issue.

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/tools/2018/why-is-the--create-symbol-files-for-current-file--option-not-ava.html

Thanks,

Regards

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.