using 7 segment display in DE1 soc

Altera_Forum · ‎05-12-2016

I am trying to use the 7 segment display of board de1 soc.

I am using linux image in an SD memory card. I could compile successful the hello.c, that has this code:

int main(int argc, char** argv) {

printf("Hello SoC FPGA!\n");

return 0;

}

Running it I could verify that my installation, I am using cross compiling on Windows, is working fine.

After I tried an example to write in 7 segment display.

I tried this code:

# define ADDR_7SEG1 ((volatile long *) 0xFF200020)

int main()

{

*ADDR_7SEG1 = 0x00000006;

}

But when I run it on the board I receive a segmentation fault .... But I don't understand why this is happening.

Somebody has some tips in what is wrong? Is there something that needs to be configured before in Hardware or Software?

Altera_Forum · ‎05-18-2016

i. Is it possible of you to tell which linux image you use?

ii. Did you add SEG module in Qsys?

iii. make sure the avalon bus to linux address mapping is corret.

iv. Did you update the rbf file?

Altera_Forum · ‎05-23-2016

i. Image I am using: DE1_SoC_SD.img

ii,iii,iv. I think I misunderstood this part in manual. I discover that what is wrong is that I am not using Qsys to add displays in FPGA .... But I didn't find in documentation a step by step where I can start on Qsys, set the FPGA to support displays and run it on linux .... Could you indicate the correct documentation accomplish this task?

Altera_Forum · ‎05-23-2016

Where from you took these values 0x00000006 and 0xFF200020 ?

Are you sure they really can be mapped within valid physical addresses ?

Altera_Forum · ‎05-23-2016

I don't remember exactly where I took this sample, but the sample from user manual didn't work too, I think is because I didn't use Qsys to set anything .... But I don't know exactly where to looking for to make this sample, or the user manual (linux) sample to work.

Altera_Forum · ‎05-24-2016

Hi ebortolini,

I am afraid no step by step instruction document for this now, maybe you could refer to the attached files here, My_First_HPS-Fpga.pdf and My_First_Fpga.pdf, and then those demo including software demo (de1_soc_traning\lab\SW\de1_soc_sw_lab3) or hardware demo (de1_soc_traning\lab\SW\de1_soc_lab3_hardware) in terasic DE1-SoC CD-ROM on resource page, for more info about SOC board design, please turn to https://rocketboards.org

Nikita

Altera_Forum · ‎05-24-2016

Hi ebortolini, sorry, I missed something attached now. Nikita