video line buffer using m9k

[Altera_Forum]

Hi all. 

I qould like to make a median filter by my own and interface it with avalon streaming protocol.  I am going to work only on Y pixelsl. Now, I need to make a line buffer of 720 pixels. Firs, I thought of something like   --- Quote Start ---   module buffer_720_brute( input clk, input [7:0] data_in, input enable, output reg[7:0] data_out ); reg [7:0] reg_1, reg_2, ..... reg 720;  always@(posedge clk) begin if (enable) begin reg_1 <= ingresso;  reg_2 <= registro_1; reg_3 <= registro_2; reg_720 <= reg_719; data_out <= reg_720; end endmodule   --- Quote End ---   I qould like to make a more efficient video line buffer, possibily using blocks or without using lots of LEs.  I was thinking of two counters, one for the write address and one for the read address, when the write adddress reaches 720 it becomes 0, while the read address begins from 0 to 720 and so on.  I fear only superpositions of read and write counter.  Could anyone please help me? Best Regards Phate.

[Altera_Forum]

Have you considered using a dual port ram or a fifo? 

In this way your 720 registers would be implemented with M9k blocks. Those two counters can directly drive the rd and wr address ports; little external logic can then be added to prevent rd/wr operation when counters match or are very close (actual action will depend from the function you need)

[Altera_Forum]

thanks for your reply. 

Yes, I was thinking of a dual prot ram, with a write enable tied up at vcc.  For the wr/read controller, I wrote something like that:   --- Quote Start ---   module controller_line_buffer (  input clk,  input reset,  input enable,   output reg [9:0] write_address,  output reg [9:0] read_address ); reg was_greater; initial begin  write_address<=10'b0;  read_address<=10'b0;  was_greater<=0;  end  always@(posedge clk ) begin  if (reset) begin   write_address<=10'b0;  read_address<=10'b0;  was_greater<=0;  end    else begin  if (enable) begin  write_address<=write_address+1'b1;  if (write_address>10'd719)was_greater <=1'b1;  if (write_address>10'd720)write_address<=10'b0;  end //end enable  if(was_greater) begin  read_address<=read_address+1'b1;  if (read_address>10'd719) read_address<=10'b0;  end//end was_greater  end//end else reset  end //end always endmodule   --- Quote End ---   But i don't find it a good controller. Any hits? Phate.