FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
5922 Discussions

viewing the de-2 board clock on the agilent 16821 logic analyzer during state-mode

Altera_Forum
Honored Contributor II
993 Views

Hi, 

 

How to view the DE-2 50 MHz clock on the waveform of 16821 Agilent Logic Analyzer during the state-mode? 

 

I use assign statement to output the DE-2 board clock to the GPIO[0] pin. Then I connect the clk pin of logic analyzer pod to the GPIO[0] pin. 

 

The DE-2 board clock can be viewed in the logic analyzer waveform thru the clk pin of logic analyzer pod during the timing-mode however during the state-mode,the clk pin of the logic analyzer pod appears to be constantly zero. 

 

I hope you guys can help me on this. 

 

Regards, 

Aish
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
304 Views

I have experience only from Tektronics logic analyzer. But there are few idea is in my head. 

 

Does the state mode need external clock or is it set to need external clk. I think timing-mode uses it's own internal clk.
0 Kudos
Altera_Forum
Honored Contributor II
304 Views

the state mode using the external clock i.e in this case, the DE2 board clock

0 Kudos
Altera_Forum
Honored Contributor II
304 Views

Do you have set clk trigger to both clock edges or can it be set this way? 

 

Can you do this kind of test where are also 25 MHz clk in captured data? 

If input clk is 50 MHz then captured data should be like "01010101"
0 Kudos
Reply