Hi,How to view the DE-2 50 MHz clock on the waveform of 16821 Agilent Logic Analyzer during the state-mode? I use assign statement to output the DE-2 board clock to the GPIO pin. Then I connect the clk pin of logic analyzer pod to the GPIO pin. The DE-2 board clock can be viewed in the logic analyzer waveform thru the clk pin of logic analyzer pod during the timing-mode however during the state-mode,the clk pin of the logic analyzer pod appears to be constantly zero. I hope you guys can help me on this. Regards, Aish
I have experience only from Tektronics logic analyzer. But there are few idea is in my head.Does the state mode need external clock or is it set to need external clk. I think timing-mode uses it's own internal clk.
Do you have set clk trigger to both clock edges or can it be set this way?Can you do this kind of test where are also 25 MHz clk in captured data? If input clk is 50 MHz then captured data should be like "01010101"