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5231 Discussions

voltage toleration for the high Z state

SZhou22
Beginner
253 Views

What is the voltage toleration for IO pin high Z state of FPGA/CPLDs? Would 15V damage the chip?

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6 Replies
Rahul_S_Intel1
Employee
119 Views

 

May I know which device is been used .

 

Rahul_S_Intel1
Employee
119 Views

Hi ,

 

 Kindly let me know, if you need further assistance.

SZhou22
Beginner
119 Views
Sorry,the Internet sucks due to some reasons.  Can you answer my question about the toleration of highs state? Take MAX V series for example. 发自我的iPhone
Rahul_S_Intel1
Employee
119 Views

Hi ,

To explain to you , with respect to max 5 , I am attaching absolute maximum rating and recommended operating conditions , these are the values which FPGA can tolerate.

The 15V will damage the FPGA

Rahul_S_Intel1
Employee
119 Views

absolute maximum rating

Rahul_S_Intel1
Employee
119 Views

Hi ,

Kindly let me know if you need further assistance

Reply