What is the voltage toleration for IO pin high Z state of FPGA/CPLDs? Would 15V damage the chip?
May I know which device is been used .
Kindly let me know, if you need further assistance.
To explain to you , with respect to max 5 , I am attaching absolute maximum rating and recommended operating conditions , these are the values which FPGA can tolerate.
The 15V will damage the FPGA
absolute maximum rating
Kindly let me know if you need further assistance
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