###########waiting for CLock in STP II analyser pls solve it###############

[Altera_Forum]

Hi all, 

 I am new to the altera fpga design systems......... I am working on a stratix II GX kit ,,,, I uaed the signal tap II analyser to see the internal signals of the design........ I used the clock as the trigger in the stp set-up.......  I compiled the code again and downloaded into the kit,,,,,,, But when i try to capture the signals its coming as waiting for clock .......  I know that clock location is having problem in my design,,,,,Can any one tell me the clock locations in the EP2SGX90FF1508C3....  I am using a single ended clock....any setting need to be done ???? Any body please help me.................

[Altera_Forum]

--- Quote Start ---  Hi all,  I am new to the altera fpga design systems......... I am working on a stratix II GX kit ,,,, I uaed the signal tap II analyser to see the internal signals of the design........ I used the clock as the trigger in the stp set-up.......  I compiled the code again and downloaded into the kit,,,,,,, But when i try to capture the signals its coming as waiting for clock .......  I know that clock location is having problem in my design,,,,,Can any one tell me the clock locations in the EP2SGX90FF1508C3....  I am using a single ended clock....any setting need to be done ???? Any body please help me.................  --- Quote End ---         Hello all,  Anybody who has worked on startix II GX 2SGX90FF1508C3 please help me in assigning the clock location....I needed help urgent... Please help me i am bit confused with the location in this device.....i am using a single ended clock... I hope this forum is to discuss problem....I know its a simple problem...Hope people are there to solve this very small problem,,,,,,,,