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what‘s’ the jitter of DDR2L/DDR3L reference clock?

TGao
Beginner
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Dear Sir/Madam

I'm choosing the Crystal oscillator for DDR(C10GX/CV)

could you help to confirm the jitter of the ddr2/3 reference clock?

Ted​

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NurAida_A_Intel
Employee
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Hi Ted,

 

Welcome to Intel Community.

 

In the EMIF handbook Vol. 2, below is the spec for PLL reference clock jitter:

The clock source of the PLL reference clock must meet or exceed the following jitter requirements:

  • 10ps peak to peak  or 1.42ps RMS at 1e-12 BER, 1.22ps at 1e-16 BER.

 

You may also refer to Cyclone 10 GX datasheet under section Table 43. Memory Output Clock Jitter Specifications for Intel Cyclone 10 GX Devices as shown below for more details. --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf

 

Jitter.PNG

 

 It is recommended to use the fastest possible PLL reference clock frequency because it leads to better jitter performance.

 

Hope this helps.

 

Thanks

 

Regards,

Aida

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TGao
Beginner
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Hi Aida, Thanks for your help! Ted
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NurAida_A_Intel
Employee
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