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will 64bit EMIF works with a 72 bits DDR4

dsun01
New Contributor III
282 Views

Dear Inter support and expert

 

I am porting a TI demo to Arria GX development board, the original design was a 64bits EMIF. and the DDR module is 72 bits. 

to make it simple, I hope I can use 64 bits EMIF directly drive a 72bits module, because I don't care the last 8 bits.  I hope this works but I am not sure, can someone who have passed this hassle give me a confirmation.

 

if I have to change the EMIF interface to 72 bits to match the DDR4 module. then how to handle the 9th byte, as all internal memory bus are based on 8 byte. 

 

Thank you very much. 

 

David 

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1 Solution
AdzimZM_Intel
Employee
264 Views

Hi David,


In case you're doing some demos, I think it's good for you to create an EMIF example design with Arria 10 Dev Kit preset where you can choose the preset in the EMIF Parameter Editor.

The preset will set the parameter that match to the Arria 10 Dev Kit.


The 72 bits = 64 bits Data + 8 bits ECC.

If you enabled the ECC in your configuration, then you will have 72 bits interface.

Else your interface should be 64 bits.


-Adzim


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7 Replies
sstrell
Honored Contributor III
272 Views

The extra byte is for error correction (ECC).  The EMIF IP supports this so you just need to enable it when parameterizing the IP.

AdzimZM_Intel
Employee
265 Views

Hi David,


In case you're doing some demos, I think it's good for you to create an EMIF example design with Arria 10 Dev Kit preset where you can choose the preset in the EMIF Parameter Editor.

The preset will set the parameter that match to the Arria 10 Dev Kit.


The 72 bits = 64 bits Data + 8 bits ECC.

If you enabled the ECC in your configuration, then you will have 72 bits interface.

Else your interface should be 64 bits.


-Adzim


dsun01
New Contributor III
260 Views

Hi AdzimZM

 

Thank you for your explanation, I have questions while I implement this 72bits EMIF qsys. If I use the presets emif_0 from Arria 10 GX FPGA Development Kit with DDR4 HILO form FPGA(72).  as in the picture, the EMIF to Avalon bus will be 576 bits. but the data from the ADC is 512 bits. where and how to convert this 512 bits data to 576 bits. 

 

Thanks 

David 

 

576 to 512 bits map question.png

dsun01
New Contributor III
255 Views

if we enable the ECC feature, then the data path to the upstream will be set to 64 instead of 72. thank you. 

AdzimZM_Intel
Employee
240 Views

Hi David,


I guess your DDR4 design is working correctly.


Kindly let me know if you're facing any error with the memory interface.


Thanks,

Adzim


dsun01
New Contributor III
230 Views

Hi Adzim

 

Yes, I do need to enable the ECC function. it works fine. thank you very much for the following up. 

 

David 

AdzimZM_Intel
Employee
209 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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