write/read sdram

[Altera_Forum]

hi, I have developed a system using sopc builder using my own component (processor) in addition to nios and other memory/peripheral devices. I am trying to write my regsiter file contents into memory(for debugging purpose). The vhdl code for this particular portion is  

 process(reg_debug, clock)  begin   if clock'event and clock = '1' then   if reg_debug = '1' then  if lock = '0' then  reg_count <= reg_count + 1;  end if;  end if;  end if;  end process;  --address hardcoded for now master_address_dmem(31 downto 0) <= "1000000100000001000000000000" & reg_count when reg_debug ='1' else .... master_writeddata_dmem <= op1_dc when reg_debug = '1' else  here is the interface to data memory which is actually sdram  master_address_dmem:OUT std_logic_vector(31 downto 0);  master_read_dmem:OUT std_logic;  master_write_dmem:OUT std_logic;  master_readdata_dmem: IN std_logic_vector(15 downto 0);  master_writeddata_dmem: OUT std_logic_vector(15 downto 0);  master_waitrequest_dmem:IN std_logic;  and I read by following  for(i=0; i < 16; i++) {  display_data = IORD_16DIRECT(SDRAM_0_BASE+0x00010000, i);   printf (...);  I always read ffff. I am not sure that whether I am unable to either read or write correctly or both.   I would be really thankful if someone could help me in fixing this problem.

[Altera_Forum]

You havent included enough of the VHDL to understand the problem. Ive no idea what op1_dc is for example. 

 Plus, you dont need reg_debug in the sensitivity list of the process.

[Altera_Forum]

Thanks for the prompt response. Op1_dc is just data to be sent be written to data. Yes, you are right, don't need reg_debug. 

 Thanks

[Altera_Forum]

basically you still havent told us enough about how its working. you need to post more VHDL - what you have posted tells us nothing.

[Altera_Forum]

Sorry for delayed response. 

Here is the interface between sdram and my processor: master_address_dmem:OUT std_logic_vector(31 downto 0); this is the address to the sdram  0 - 0x0000FFFF space is used for data 0x0001FFFF - onward is reserved for debug symbol i,e; for dumping register contents. The following process reads the register contents when reg_debug (dip switch) is asserted. The reg_count is index to register file and reg_count is also contacted to data memory address as a least signifcant nibble. process(reg_debug, clock)  begin   if clock'event and clock = '1' then   if reg_debug = '1' then  if lock = '0' then  reg_count <= reg_count + 1;  end if;  end if;  end if;  end process;  lock <= master_waitrequest_pmem or master_waitrequest_dmem;  master_read_dmem:OUT std_logic; This the data memory read signal is asserted when loading from the memory.   master_write_dmem:OUT std_logic; asserted when writing to memory (when storing or debugging ) master_write_dmem <= data_mem_wr_en or reg_debug or pc_debug; pc-debug is also connected to a dip switch   master_readdata_dmem: IN std_logic_vector(15 downto 0); data returned from data memory.   master_writeddata_dmem: OUT std_logic_vector(15 downto 0); data to be written to data memory  master_writeddata_dmem <= op1_dc when reg_debug = '1' else -- writing register file contents   pc(15 downto 0) when pc_debug = '1' else -- wrting pc halfword  data_to_data_mem; -- normal writing to data memory.  master_waitrequest_dmem:IN std_logic; this wait signal locks the processor and freezes all synchornous processes.  I hope that this explanation will help in understanding my problem. If you need any particular portion of VHDL portion, kindly indicate.  Thanks