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10-Gbps Ethernet MAC MegaCore Migration Guideline

10-Gbps Ethernet MAC MegaCore Migration Guideline

Last Major Update

October 09, 2012


Altera released the first 10-Gbps Ethernet Reference Design with XAUI interface back in November 2008. Over the years, the reference design has been upgrated with new feature and Altera FPGA device support. However, Altera no longer maintain and upgrete the reference design after Altera Complete Design Suite (ACDS) 11.0 release. 

In 2010, Altera had launch several new 10-Gbps Ethernet MegaCore such as:

  • Ethernet 10G MAC
  • 10G Base-R PHY

Besides, Altera also release the Altera Ethernet 10G Design Example in QSYS to simplfied the integration process between Ethernet 10G MAC, PHY IP, FIFO, and etc. The Altera new 10-Gbps Ethernet MegaCores support the latest Altera FPGA device family such as Stratix V, Arria V and Cyclone V.

For more information regarding the 10-Gbps Ethernet Reference Design refer to here.

For more information regarding the new 10-Gbps Ethernet MegaCore refer to:


The main object of this page is to provide some comparison overview and migration guidance from the 10-Gbps Ethernet Reference Design to the new 10-Gbps Ethernet MegaCore. 

Migration Guideline

Table below shows the similar MegaCore combination with regard to the 10-Gbps Ethernet Reference Design.

10-Gbps Ethernet Reference DesignMegaCore CombinationQSYS
MAC + XGMII10-Gbps Ethernet MAC MegaCore + DDIO MegaCore-
MAC + XAUI10-Gbps Ethernet MAC MegaCore + XAUI PHY IP MegaCore10Gbps MAC Design Example
MAC Only10-Gbps Ethernet MAC MegaCore10Gbps MAC Design Example
XAUI OnlyXAUI PHY IP MegaCore10Gbps MAC Design Example

Please take note that 10Gbps MAC Design Example in the QSYS system include the single-clock and dual-clock FIFO combination and MDIO whereas the FIFO and MDIO is NOT part of the 10-Gbps Ethernet MAC MegaCore and XAUI PHY IP MegaCore.

Before start migrating to the new Ethernet MegaCores, please ensure you understand the differences in the following area:

  • Installation
  • Architecture
  • IP Core Parameterization and Features
  • Interfaces
  • Configuration Register
  • Timing Constraints

Download the following document for the detail comparison and guidline between the 10-Gbps Ethernet Reference Design and Ethernet MegaCores.

10-Gbps Ethernet MAC and PHY MegaCore Migration Guideline.doc


  1. 10-Gbps Ethernet Reference Design User Guide
  2. 10-Gbps Ethernet MAC MegaCore Function User Guide
  3. Altera Transceiver PHY IP Core User Guide
  4. Embedded Peripherals IP User Guide
  5. AN588: 10-Gbps Ethernet Hardware Demonstration Reference Design
  6. AN638: 10-Gbps Ethernet MAC and XAUI PHY IP Interoperability Hardware Demonstration Reference Design
  7. 10-Gbps Ethernet IP Core Resource Center


© [2012] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

Version history
Last update:
‎06-26-2019 02:41 PM
Updated by: