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100Gbps Ethernet 10x10 MAC PHY IP CFP Hardware Demo Design

100Gbps Ethernet 10x10 MAC PHY IP CFP Hardware Demo Design

Title

100G Ethernet 10x10 MAC-PHY IP Hardware demo design on 100G Stratix V GX Development Board

Introduction

This reference design demonstrates the operation of Altera® 100-Gbps Ethernet MAC and PHY IP solution on a Stratix V GX device (5SGXEA7N2F45C2). It is configured to demonstrate on a Stratix V GX 100G Development Board using Altera development tool Quartus II release 15.0. This design provides a flexible test and demonstration platform which effectively control, test, and monitor 100Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP module with 10 x 10Gbps full-duplex channels.

This hardware demonstration reference design offers the following features:

  • Stand-alone and easy-to-use reference design example with flexibility to dynamically select traffic profile.
  • Uses a standard 512-bit Avalon-ST interface to connect to the Ethernet Traffic Generator.

- Compare packet statistics at Transmit and receive MACs.

- Check for Hardware errors in the MAC & PHY.

- Check for CRC error in the Rx MAC.

  • 32-bit Avalon-MM interface to do register access.
  • System console and TCL based flexible, reusable, and extendable user interface allows users to dynamically configure various registers provided by this demo design.

System Overview

The hardware platform consists of three sub-systems:

  • The 100G Ethernet MAC & PHY IP

- Built in different packet counters including error packet counts

- Built in Tx to Rx serial loopback function

- Built in PRBS generator and checker

  • Traffic Generator

- Packet generator

- Packet monitoring

- Configurable packet header and payload

- Rx to Tx parallel loopback function

  • TCL based System Controller for configuration and control of the system

- GUI control interface

This system can be represented by the following diagram: f/fa/100G_CAUI_system.jpg


100G Ethernet MAC & PHY IP

The Altera 100G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 803.3ba 2010 Higher Speed Ethernet Standard. This module handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 100GbE Ethernet PCS and PMA. In the TX direction, the MAC accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header, padding, and checksum before passing them to the PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end. Similarly, in the RX direction, the MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client.

The 40G Ethernet sub-system consists of 40G MAC and PHY sub-modules. The MAC client side data path interface has two options: Avalon ST interface and Custom ST interface. This reference design uses an Avalon-ST interface which includes interface adapter. This adapter then provides a standard Avalon-ST interface for the MAC client. The MAC connects to the PHY core over XLGMII interface. The 40G Ethernet IP core can be demonstrated as the following simplified diagram: 6/66/MACandPHY.jpg


The additional details of the IP core can be found in the User guide. The IP core evaluation package and the user guide can be downloaded from www.altera.com

Packet Client

The traffic controller includes a Packet Generator and Packet monitor. These modules have 512-bit Avalon-ST interface for the data-path and connect to the 100G Ethernet MAC. There is also a 32-bit Avalon-MM configuration and status interface associated with the Generator. The generator can generate packets with random size from 64 Bytes to 1500 Bytes.

System Controller

The system controller uses TCL based Altera SYSTEM-CONSOLE which can run on a PC with either a Linux or windows based operating system. The details on system-console can be found in: System Console User Guide. User must provide byte addresses in order to access registers on chip using this interface.

Start Guide for Hardware Demo design

The reference design setup essentially consists two parts:

  • Stratix V GX Transceiver SI Evaluation Board hardware setup (Use default setting)
  • Quartus II 15.0 and System Console Terminal setup

The relevant setups for each of these components are provided in detail as shown below:

Stratix V GX Transceiver SI Evaluation Board Hardware Setup

The Stratix V GX Transceiver SI Evaluation Board requires minimum hardware setup. A onetime setting is required to ensure the following:

  1. The CFP is connected to an optical loopback cable, or use PMA internal loopback.
  2. The DIP switches should not change. Use the default setting.

Before turning on power switch at the upper left corner of the development board, three cables need to be connected into development kit:

  1. Power supply cable with adaptor to provide 15V - 20V DC voltage.
  2. USB blaster cable connected between PC and evaluation board.
  3. An optical loopback cable is installed tightly into the CFP module.

e/e3/100GDK.jpg

Quartus II Project Setup

  1. Download the SV_100G_Ethernet_15.0.zip
  2. Navigate File -> Open project -> /SV_100G_Ethernet_15.0/gen_100_example/alt_e40_e100/example/alt_e100_avalon_top_sv.qpf
  3. Use programmer to download alt_e100_avalon_top_sv.sof file onto the FPGA.

System Console Terminal Setup

  1. Navigate to Tools -> System Debugging Tools -> System Console.
  2. “cd system_console” to change the directory.
  3. “source main_run.tcl” to execute the script.

2/2a/System_console.jpg

System Console GUI Control Panels

1. Packet Generator: Random Packet Generator.

d/d1/PacGen.png

2. Packet Monitor: It includes “Send Random Packet” and “Stop sending packets”.

2/2c/PacMon.png

3. System Control: a. Example of internal PMA loop back

i. Internal Serial Loopback ON //set tx to rx loopback mode

ii. Send Random Packet //run start

iii. Stop Sending Packets //stop

iv. Update //display tx and rx statistics

b. Example of parallel loopback

i. Parallel RX to TX Loopback ON //make sure Serial Loopback OFF

ii. Program registers 0x127 to 0x1 and 0x126 to 0x200. This will fix the PPM difference issue

iii. Follow steps ii to iii from the above example to test

c/ca/SysCon.png

4. System Monitor: Example of case showing linkup without any error.

c/c9/SysMon.png

System Console available commands

  • reg_read 0x1010 //Read register
  • reg_write 0x1010 0x0 //Write register

Pass and Fail Check

All error counts should equal to 0. In the loopback test case: number of Ethernet frames or total data transmitted should equal to number of frames or total data received and all error Ethernet frame counters should equal to 0. See “Example of internal PMA loop back test passed case” below. Fail condition in the loopback test: Any of error Ethernet frame counter is NOT equal to 0, total data transmitted not equal to received, or number of frames transmitted not equal to received are consider fail case.

c/c9/System_Console_Counter.png

Download Design

SV 100G Ethernet 15.0.zip

The above zip contains all files used in design, except the db and incremental_db folders. In order to obtain the full package, just recompile the alt_e100_avalon_top_sv.qpf in Quartus II 15.0.

Quartus II 14.0 version Alt e100 avalon 10x10 hw demo.zip

Reference links

Altera 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide (PDF)

Altera 100G Development Kit, Stratix V GX Edition (PDF)

Known Issue

Please note that the system is flexible testing platform. We have done a limited number of testing with an intention to demonstrate the inter-op of the two sub-systems. Additional test cases can be created by creating various kind of difference setting to the sub-system. Also note that the system console and TCL based scripting provides a flexible testing platform. We have done a limited number of testing with an intention to demonstrate the inter-op of the two sub-systems. Additional test cases can be created by creating various kind of difference setting to the sub-system.

History

Last Update: August 4, 2015

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Last update:
‎06-26-2019 02:45 PM
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