100G Ethernet 10x10 MAC-PHY IP Hardware demo design on 100G Stratix V GX Development Board
This reference design demonstrates the operation of Altera® 100-Gbps Ethernet MAC and PHY IP solution on a Stratix V GX device (5SGXEA7N2F45C2). It is configured to demonstrate on a Stratix V GX 100G Development Board using Altera development tool Quartus II release 15.0. This design provides a flexible test and demonstration platform which effectively control, test, and monitor 100Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP module with 10 x 10Gbps full-duplex channels.
- Compare packet statistics at Transmit and receive MACs.
- Check for Hardware errors in the MAC & PHY.
- Check for CRC error in the Rx MAC.
- Built in different packet counters including error packet counts
- Built in Tx to Rx serial loopback function
- Built in PRBS generator and checker
- Packet generator
- Packet monitoring
- Configurable packet header and payload
- Rx to Tx parallel loopback function
- GUI control interface
This system can be represented by the following diagram: f/fa/100G_CAUI_system.jpg
The Altera 100G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 803.3ba 2010 Higher Speed Ethernet Standard. This module handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 100GbE Ethernet PCS and PMA. In the TX direction, the MAC accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header, padding, and checksum before passing them to the PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end. Similarly, in the RX direction, the MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client.
The 40G Ethernet sub-system consists of 40G MAC and PHY sub-modules. The MAC client side data path interface has two options: Avalon ST interface and Custom ST interface. This reference design uses an Avalon-ST interface which includes interface adapter. This adapter then provides a standard Avalon-ST interface for the MAC client. The MAC connects to the PHY core over XLGMII interface. The 40G Ethernet IP core can be demonstrated as the following simplified diagram: 6/66/MACandPHY.jpg
The additional details of the IP core can be found in the User guide. The IP core evaluation package and the user guide can be downloaded from www.altera.com
The traffic controller includes a Packet Generator and Packet monitor. These modules have 512-bit Avalon-ST interface for the data-path and connect to the 100G Ethernet MAC. There is also a 32-bit Avalon-MM configuration and status interface associated with the Generator. The generator can generate packets with random size from 64 Bytes to 1500 Bytes.
The system controller uses TCL based Altera SYSTEM-CONSOLE which can run on a PC with either a Linux or windows based operating system. The details on system-console can be found in: System Console User Guide. User must provide byte addresses in order to access registers on chip using this interface.
The reference design setup essentially consists two parts:
The relevant setups for each of these components are provided in detail as shown below:
The Stratix V GX Transceiver SI Evaluation Board requires minimum hardware setup. A onetime setting is required to ensure the following:
Before turning on power switch at the upper left corner of the development board, three cables need to be connected into development kit:
1. Packet Generator: Random Packet Generator.
2. Packet Monitor: It includes “Send Random Packet” and “Stop sending packets”.
3. System Control: a. Example of internal PMA loop back
i. Internal Serial Loopback ON //set tx to rx loopback mode
ii. Send Random Packet //run start
iii. Stop Sending Packets //stop
iv. Update //display tx and rx statistics
b. Example of parallel loopback
i. Parallel RX to TX Loopback ON //make sure Serial Loopback OFF
ii. Program registers 0x127 to 0x1 and 0x126 to 0x200. This will fix the PPM difference issue
iii. Follow steps ii to iii from the above example to test
4. System Monitor: Example of case showing linkup without any error.
All error counts should equal to 0. In the loopback test case: number of Ethernet frames or total data transmitted should equal to number of frames or total data received and all error Ethernet frame counters should equal to 0. See “Example of internal PMA loop back test passed case” below. Fail condition in the loopback test: Any of error Ethernet frame counter is NOT equal to 0, total data transmitted not equal to received, or number of frames transmitted not equal to received are consider fail case.
The above zip contains all files used in design, except the db and incremental_db folders. In order to obtain the full package, just recompile the alt_e100_avalon_top_sv.qpf in Quartus II 15.0.
Quartus II 14.0 version Alt e100 avalon 10x10 hw demo.zip
Please note that the system is flexible testing platform. We have done a limited number of testing with an intention to demonstrate the inter-op of the two sub-systems. Additional test cases can be created by creating various kind of difference setting to the sub-system. Also note that the system console and TCL based scripting provides a flexible testing platform. We have done a limited number of testing with an intention to demonstrate the inter-op of the two sub-systems. Additional test cases can be created by creating various kind of difference setting to the sub-system.
Last Update: August 4, 2015