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100Gbps Ethernet MACPHY IP reference design

100Gbps Ethernet MACPHY IP reference design


Last Major Update 

June 6, 2013

 

Downloadable Reference Design File

Altera 100-Gbps Ethernet MAC and PHY IP Hardware Demonstration Design for Loopback Test on Stratix V...


Reference Documents

Altera 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide (PDF) 

Altera 100G Development Kit, Stratix V GX Edition (PDF) 


Introduction

 This reference design demonstrates the operation of Altera® 100-Gbps Ethernet MAC and PHY IP solution on a Stratix V device (5SGXEA7N2F45C2). It is configured to demonstrate on a 100G Development Kit, Stratix V GX Edition Board using Altera development tool Quartus II release 12.1. 

This design provides a flexible test and demonstration platform which effectively control, test, and monitor 100Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP module with 10 full-duplex channels.


This hardware demonstration reference design offers the following features:

• Stand-alone and easy-to-use reference design example with flexibility to dynamically select traffic profile.

• Uses a standard 512-bit Avalon-ST interface to connect to the Ethernet Traffic Generator and Monitor.

• Provides packet statistics for Generator and Monitor at the end of each test to further confirm the test result. 

• Provides throughput measurement for the packet data received by the monitor.

• System console and TCL based flexible, reusable, and extendable user control interface allows users to dynamically configure and monitor any configuration registers provided by this demo design.


System Overview and Functional Description

The hardware platform consists of three sub-systems: 

• The 100G Ethernet MAC and PHY IP

• Traffic controller with packet Generator and Monitor

• TCL based System Controller for configuration and control of the system


This system can be represented by the following diagram:

a/a2/100G_CAUI_system.png

 


100-Gbps Ethernet MAC and PHY IP

The Altera 100G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 803.3ba 2010 Higher Speed Ethernet Standard. This module handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 100GbE Ethernet PCS and PMA (PHY). In the TX direction, the MAC accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header, padding, and checksum before passing them to the PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end. Similarly, in the RX direction, the MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client.

Traffic Controller with Packet Generator (GEN) and Monitor (MON)

The traffic controller includes a Packet Generator and a Packet Monitor. These modules have 512-bit Avalon-ST interface for the data-path and connect to the 100G Ethernet MAC. There is also a 32-bit Avalon-MM configuration and status interface associated with both the Generator and the Monitor. The generator can be configured to generate packets with size from 64 Bytes to 1500 Bytes. The user can also configure the generator to create a burst of packet with up-to 64K packets. Traffic monitor parses all packets received from MAC and checks the integrity of the packets and collects various statistics including number of good and bad packets received.

TCL Based System Controller

The system controller uses TCL based Altera SYSTEM-CONSOLE which can run on a PC with either a Linux or windows based operating system. The details on system-console can be found in:system console user guide. User must provide byte addresses in order to access registers on chip using this interface.



100Gbps Ethernet MAC and PHY IP Overview

As mentioned in previous sections, the 100G Ethernet sub-system consists of 100G MAC and PHY sub-modules. The MAC client side data path interface has two options: Avalon ST interface and Custom ST interface. This reference design uses an Avalon-ST interface which includes interface adapter. This adapter then provides a standard Avalon-ST interface for the MAC client. The MAC connects to the PHY core over CGMII interface. The 100G Ethernet IP core can be demonstrated as the following simplified diagram: 6/66/MACandPHY.jpg

 


Additional Functional Details of 100GE Ethernet IP Core

The additional details of the IP core can be found in the User guide. The IP core evaluation package and the user guide can be downloaded from Altera website: http://www.altera.com/products/ip/iup/ethernet/m-alt-40-100gb-ethernet.html


Quick Start Guide

The reference design setup essentially consists of two parts:

• 100G Stratix V GX development board hardware setup • 100G Development Kit – Stratix V GX Edition v11.1.2 setup • Quartus II 12.1 and SignalTap II Logic Analyzer setup • Windows based sterm Terminal System Controller setup

The relevant setup for each of these components are provided in detail as shown below:


100G Stratix V GX Development Kit Hardware Setup

The 100G Stratix V GX development kit requires minimum hardware setup. A one time setting is required to ensure the following:

1. The CFP is connected to an optical loopback cable

2. The DIP switches shown on the right side of the board (in the picture below) are pushed towards the edges of the PCB (tied low). These switches were used only during the development to debug the correct settings of CFP controls and are not required to be changed by the user. 

3. The MSEL Pin settings switch SW2 should read MSEL [4:0] = 00100

4. The SW3 should read 7:0 = 1101111

5. The Fan bypass and MAX_JTAG_EN jumpers J9 and J62 shunt positions should be Not Installed. 


Before turning on power switch at the upper left corner of the development kit, three cables need to be connected into development kit:

1. Power supply cable with adaptor to provide 19V DC voltage.

2. USB blaster cable connected between PC and development kit.

3. An optical loopback cable is installed tightly into the CFP module.

  e/e3/100GDK.jpg

100G Development Kit - Stratix V GX Edition v11.1.2 Setup

Install the 100G development kit – Stratix V GX Edition v11.1.2 from 100G Development Kit, Stratix V GX Edition Board which is required for Clock Control for the 100G Stratix V GX development board.

Open the Clock Control application and read the U53 Si5338 registers. U53 Si5338 oscillator supplies the pins AF6/AF7 which is connected to reference input clock. Confirm clock setting as Clk2 at 644.5313 and CLK3 at 100.00.

4/46/40Ge_cc1.jpg


Quartus II 12.1 and SignalTap II Logic Analyzer Setup

1. Open the alt_e40_avalon_top_sv.qar as project in Quartus II 12.1 subscription edition, it will ask to restore the project. Check for proper names and directories. As soon as the unarchiving is complete the project alt_e40_avalon_top_sv.qpf will be loaded. The designed is compiled and already has alt_e40_avalon_top_sv.sof to be downloaded on development board.

2. Open the SignalTap II Logic Analyzer by double clicking on stp1.stp from files tab in project navigator. The TX and RX signals to be monitored are already added to the instance.

3. Program the board from SignalTap II Logic Analyzer. The MAX_JTAG_EN jumpers J62 shunt position should be Installed. On successful operation the Instance Manager will show “Ready to acquire”.

Windows Terminal Setup

Navigate to utility/terminal64 directory and open the sterm.exe

The following should appear.


5/51/40Ge_check.jpg

1. Execute the following commands to verify clocks

a. reg_read 0x0002 //to read CLK_TXS giving 257,xxx KHz

b. reg_read 0x0003 //to read CLK_RXS giving 257,xxx KHz

c. reg_read 0x0004 //to read CLK_TXC giving 315,xxx KHz

d. reg_read 0x0005 //to read CLK_TXC giving 315,xxx KHz


b/b3/40Ge_clk_chk.jpg

2. Execute the following commands to perform External Optical Loopback.

a. reg_read 0x1010        //to read the enable register triggering the traffic generator

b. reg_write 0x1010 00000001 //to set the enable register triggering the traffic generator to generate packets.

c. reg_read 0x1010        //to verify the above write operation


0/04/40Ge_ext_opt_loopback.jpg

OR


2. Execute the following commands to perform Internal Serial Loopback.

a. reg_read 0x1010        //to read the enable register triggering the traffic generator

b. reg_write 0x1010 00000001 //to set the enable register triggering the traffic generator to generate packets.

c. reg_read 0x1010        //to verify the above write operation

d. reg_read 0x0061        //to read the register enabling the internal serial loopback of TX and RX

e. reg_write 0x0061 ffffffff    //to set the register enabling the internal serial loopback of TX and RX

f. reg_read 0x0061         //to verify the above write operation*

*(getting back 0000000f indicates proper write operation and set of proper register)

3/37/40Ge_int_ser_loopback_on.jpg


SignalTap II Logic Analyzer instance waveform verification

Click on Autorun Analysis to acquire waveform on the data tab. You can verify the status of various signals from the MegaCore function user guide.


/64/40Ge_SignalTapII.jpg

Hardware demo design Package

Reproducing the hardware demo design can be done at various levels of the development flow. A quick regeneration of SOF file needs compilation and regeneration of the files provided with the download. The downloaded archive file consists of the following sub-directories under top level directory: 100G_SV_REL12.1.

1. alt_e100_avalon_top_sv/example_design – it contains RTL files for Ethernet and other logic blocks

2. example_testbenches - directory that contains compile and simulation run scripts

3. Utility/terminal64 – windows based sterm Terminal System Controller

Running Simulation

Unzip and populated the 100G Ethernet demo design. The demo design provides a test bench in the verif directory and scripts is sim directory necessary to compile and run a simulation. Please follow the following steps to perform the simulation.

1. Start the Modelsim tool

2. Go to alt_e100_avalon_top_sv/gen_100_example/example_testbenches/SV_alt_e100_avalon_tb/vsim in command prompt

3. On the command window execute vcs –c –do run_vsim.do and watch for messages until the process is complete.

4. At the end of the simulation the tool will provide a summary of how many packets received with Error.

Similarly execute other EDA scripts for simulations.

Compile the design

Please follow the following steps to recompile the design.

1. Go to the 100G_SV_REL12_1/quartus directory where CHIP.* files are located

2. Start Quartus 12.1 software. Please do not create any project.

3. Open the alt_e100_avalon_top_sv.qpf file provided with the design.

4. Upon a successful load, start comprehensive compile and wait for the process to finish.

5. At the end of the compile, SOF file is generated. 

Known Issue

Please note that the system console and TCL based scripting provides a flexible testing platform. We have done a limited number of testing with an intention to demonstrate the inter-op of the two sub-systems. Additional test cases can be created by creating various kind of difference setting to the sub-system.

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Last update:
‎06-26-2019 02:49 PM
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