April 25th, 2014
This reference design demonstrates the operation of Altera® 100-Gbps Ethernet MAC and PHY IP solution on a Stratix V GT device (5SGXEA7N2F45C2). It is configured to demonstrate on a Stratix V GX 100G Development Board using Altera development tool Quartus II release 13.0sp1.
This design provides a flexible test and demonstration platform which effectively control, test, and monitor 100Gbps Ethernet packets using internal serial PMA loopback and external optical loopback through CFP module with 10 x 10Gbps full-duplex channels.
Note: The hardware demo design is for demo only. If you want to run line rate test, please contact your local Altera sales.
• Stand-alone and easy-to-use reference design example with random packet types and size, fix packet size back to back mode, fix packet size burst mode, fix packet monitor and configurable parameter.
• Uses a standard 512-bit Avalon-ST interface to connect to the Ethernet Traffic Generator. Compare packet statistics at Transmit and receive MACs.
Check for Hardware errors in the MAC & PHY
Check for CRC error in the Rx MAC
• 32-bit Avalon-MM interface to do register access
• System console and TCL based flexible, reusable, and extendable user interface allows users to dynamically configure various registers provided by this demo design.
The Altera 100G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 803.3ba 2010 Higher Speed Ethernet Standard. This module handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 100GbE Ethernet PCS and PMA. In the TX direction, the MAC accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header, padding, and checksum before passing them to the PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end. Similarly, in the RX direction, the MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client.
The traffic controller includes a Packet Generator. These modules have 512-bit Avalon-ST interface for the data-path and connect to the 100G Ethernet MAC. There is also a 32-bit Avalon-MM configuration and status interface associated with the Generator. The generator can generate packets with random size from 64 Bytes to 1500 Bytes or fixed size packet from 64 Byte to 20200 Byte.
All error counts should equal to 0. In the loopback test case: number of Ethernet frames or total data transmitted should equal to number of frames or total data received and all error Ethernet frame counters should equal to 0. See “Example of internal PMA loop back test passed case” below.
Fail condition in the loopback test: Any of error Ethernet frame counter is NOT equal to 0, total data transmitted not equal to received, or number of frames transmitted not equal to received are consider fail case.
Example of internal PMA loop back test passed case
The system controller uses TCL based Altera SYSTEM-CONSOLE which can run on a PC with either a Linux or windows based operating system. The details on system-console can be found in: System Console User Guide. User must provide byte addresses in order to access registers on chip using this interface.
As mentioned in previous sections, the 40G Ethernet sub-system consists of 40G MAC and PHY sub-modules. The MAC client side data path interface has two options: Avalon ST interface and Custom ST interface. This reference design uses an Avalon-ST interface which includes interface adapter. This adapter then provides a standard Avalon-ST interface for the MAC client. The MAC connects to the PHY core over XLGMII interface. The 40G Ethernet IP core can be demonstrated as the following simplified diagram: 6/66/MACandPHY.jpg
The additional details of the IP core can be found in the User guide. The IP core evaluation package and the user guide can be downloaded from Altera website.
The reference design setup essentially consists two parts:
The relevant setups for each of these components are provided in detail as shown below:
The Stratix V GT Transceiver SI Evaluation Board requires minimum hardware setup. A one time setting is required to ensure the following:
1. The CFP is connected to an optical loopback cable, or use PMA internal loopback.
2. The DIP switches should not change. Use the default setting.
Before turning on power switch at the upper left corner of the development board, three cables need to be connected into development kit:
1. Power supply cable with adaptor to provide 15V - 20V DC voltage.
2. USB blaster cable connected between PC and evaluation board.
3. An optical loopback cable is installed tightly into the CFP module.
To run Windows or Linux based system console; Quartus II rev13.0 software must be installed to execute system-console utility.
Turn on power supply after connecting the development kit using a USB blaster cable to PC and follow below steps to run test:
1. Download the “Alt_e100_10x10_hw_demo_cfp_13_0sp1.qar”.
2. Open Alt_e100_10x10_hw_demo_cfp_13_0sp1.qar file with Quartus II rev13.0 software. Select your work directory.
3. Use Quartus II rev13.0 software Programmer to download alt_e100_avalon_top_sv.sof file into FPGA.
4. Go to the “Tools” –> “Transceiver Toolkit” menus in Quartus II rev13.0sp1 software. It will open up the System Console tool.
5. Close two Transceiver Toolkit windows.
6. Type "cd system_console" press enter. Type "source main_run.tcl" to execute the script.
7. Press the S6 (CPURSTn) bottom. Now the platform is ready to run.
1. PacketGenerator: Random and fix packet generator.
Note: Stop the traffic first before change between random and fix packet.
2. PacketMonitor: It also including short cut of “Send Random Packet”, “Send Fixed Packet” and “Stop Sending Packets”.
3. SystemControl: Example of internal PMA loop back
Step1: loop_on //Set tx to rx loopback mode
Step2: run // Start generate random size packets
Step3: stop // Stop the traffic and display TX and RX status
4: SystemMonitor: A good case of linkup without any error.
reg_read 0x1010 //Read register
reg_write 0x1010 0x0 //Write register
Reproducing the hardware demo design can be done at various levels of the development flow. A quick regeneration of SOF file needs compilation and regeneration of the files provided with the download. The downloaded archive file consists of the following sub-directories under top level directory: alt_e100_avalon_10x10_hw_demo_13_0sp1_restored.
1. gen_100 – it contains RTL files for Ethernet and other logic blocks
2. common – includes the top level and related include files
3. system_console –TCL scripts file
Please note that the system console and TCL based scripting provides a flexible testing platform. We have done a limited number of testing with an intention to demonstrate the inter-op of the two sub-systems. Additional test cases can be created by creating various kind of difference setting to the sub-system.