10Gbps Ethernet MAC Debug Checklist

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10Gbps Ethernet MAC Debug Checklist

10Gbps Ethernet MAC Debug Checklist

Last Major Update 

February 14, 2015



The objective of the wiki page is to provide a useful debug guideline and checklist which help to debug and identify issue related to Altera 10Gbps Ethernet MAC Megacore in order to resolve it effectively.

10Gbps Ethernet MAC Architectures & Signals comparison

Architectures: 7/74/10GbE_MAC_Architecture_comparison_1.png





MAC + PHY Ethernet Solution

In a MAC + PHY Ethernet System, how to identify the issue: User Error? PHY Issue? MAC Issue? 



Thus, we need a proper Debug Checklist or guidance in order to root cause the issue. 

Debug Checklist

Things to do before start debugging:

1. Understand the problem statement/requirement. 

2. ACDS Version/IP Version/Target Device/LL MAC IP variants (Speed variant, adapters enable/disable, etc) 

3. Check Fogbugz/KDB/Errata.

4. Crosscheck with the IEEE 802.3 Specification and Avalon Specification 

5. MAC IP variants

- 10G, 1G/10G or multi-speed 10M-10G.

- MAC Options: supplementary Address, CRC on transmit Path, Statistic counter,Preamble pass-through mode, PFC.

- TIPS1: Get the 10G Verilog/VHDL Wrapper that generated by the Megawizard.

6. Configuration Register Settings

7. Timing Closure – hardware issue

8. Debug Information

- Hardware vs. Simulation 

-Failing symptom: Intermittent or consistent

-Transmitter issue vs Receiver issue

9. Simplify design or test case if necessary

10. Follow the debug flow(as shown below).

Debug Flow -10G Ethernet Issue


Debug Step - 1st Level Check

■ Ensure all signals connected to MAC IP appropriately.

-Avalon-ST , Avalon-MM, SDR XGMII, GMII, MII interfaces

■ Ensure all clocks are operating at their specified frequencies.

-tx_clk, rx_clk, gmii_tx_clk, gmii_rx_clk, csr_clk

■ Ensure all resets are released and clocks are available.

■ Transmitted /Received input data are available.

■ Make sure no timing violation and clocks are constraint correctly. 

Example of correct MAC+PHY connection�10G MAC + XAUI/10G Base-R PHY Interface



Clock Frequency for 10G Ethernet System


Debug Step - 2nd Level Check


If the problem cannot be solved with 1st level debug check , please follow the 2nd level debug check:  

■ Always look at the interface to identify the error.


-Avalon MM


-Status signals (Speed_sel, link_fault_status, led_link,pll_locked, rx_data_ready)

-Always read out MAC Transmit /receive statistic counter to identify the packet condition sent/received by MAC.

■ Perform MAC local loopback to verify the functionality of the MAC. 

■ Perform MAC+PHY serial loopback 

■ Replicate issue with ACDS design example /Reference design 

TIPS 2: Always get some data for analysis

-Gather all the information and compare with the expected

- User guide descriptions

- IEEE802.3 Specification

- Avalon-ST protocol

- UNH test plan

- Simulation result

-Duplicate the issue in house with ACDS example design / Reference design published on altera-wiki web.

- “..\ip\altera\ethernet\altera_eth_10g_design_example”

These example designs and reference designs can be used as a common entity for simulation and hardware verification purposes.

Case Studies

Case Study 1

  • Problem Statement:

- Packet sent on Avalon Streaming interface to MAC but no data received by PHY

  • Debug Steps:

1. Check MACPHY XGMII interface signals, no data sent out from MAC.

2. Check Link Fault status signal, value 01 (Local Fault).Local fault happens, all data sent by client user logic are dropped.

-Avalon ST TX and RX input/output signals to Avalon ST TX/RX 64 bit adapter

TIPS 3 : Before transmitting any data, make sure the link is ready:

1. rx_data_ready = 1'b1

2. link_fault_status_xgmii_rx_data = 2'b00

Case Study 2

  • Problem Statement:

- MAC registers Write/Read issue:

Failed to read back rx_pfc_control register value 


MAC statistic counter read back wrong value 



  • Debug steps:

1.Check MAC variant:


Root Cause: Due to resource optimization, register logic is being optimized away because the feature is not available. Unexpected result obtained.

TIPS 4: Ensure Statistic collection and priority flow control option are enabled before try to access the related registers. 

Case Study 3

  • Problem Statement:

- Ethernet failed to change speed:


  • Debug steps:

1.Check Avalon-MM interface

Root Cause: Write to PHY 0x2c0 register for speed change during rc_busy period.


TIPS 5: Expected simulation for ethernet speed changes from 10G to 1G to 100Mto 10M 




-Debug the 10G MAC IP can be easy if follow a proper debug steps.

-Remember the recommended items in the checklist before debugging.

-Follow the 5 tips provided.

Letzte Aktualisierung:
‎06-26-2019 02:55 PM
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