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1536-point FFT for 3GPP LTE Radio Design - VHDL

1536-point FFT for 3GPP LTE Radio Design - VHDL


Last Major Update

September 30, 2010

Overview

Altera provides lots of Application Notes (AN) designed to show design engineers how to do certain functions. However, those ANs that include an FPGA design are most commonly delivered in Verilog, and rarely in VHDL. This may be a challenge for you if you are using a single language ModelSim Altera Edition for your design simulation. If your supported HDL language doesn’t match the language used in the AN, you will have to do a conversion.

The HDL conversion efforts can be especially challenging when complex MegaCore functions with simulation models are used in the design. Additionally, DSP related ANs will often use File I/O in the top level Testbench in order to stimulate/verify the HDL design with Matlab. Converting File I/O operations from Verilog to VHDL (and vice versa) can be very confusing because there are lots of ways to do this that all give different results (binary/ascii files, formatting, etc).

In this application example, I’ve converted the existing Application Note for a 1536-point FFT for 3GPP LTE radio design (AN480) from Verilog to VHDL. 3GPP is getting more attention recently by wireless and military customers. The current AN480 is written entirely in Verilog and uses Matlab to generate input data files and do bit-for-bit verification of output files written by a Verilog Testbench. I’ve created a functionally equivalent pure VHDL version of the design, including the File I/O and Matlab interaction. I’ve kept the design structure the same as much as possible, including process/module structure, signal and port names, etc. The Quartus II project now has two revisions, one for Verilog and one for VHDL. In addition, the Verilog and VHDL source directories have been kept separate to allow you to easily compare/contrast the two implementations, and choose the one that best matches your existing tool flow.


Block diagram

c/c0/1536FFT_verilog_block.png


1536FFT verilog block.png


Processing Block Description

lcd_input

De-serialize and unpack LVDS input bus to parallel RGB data

Extract video frame syncs

Encode video data into Avalon Streaming Video Packets

Provide backpressure enabled FIFO interface

Scaler

Bicubic scaling function to scale from 800x480 to 1024x600

lcd_output

Provide backpressure enabled FIFO interface for Avalon ST Video 

Decode Avalon ST Video Packets to raw video and syncs

Insert video syncs back into data stream

Pack and serialize video data into x7 LVDS output bus

Design Notes

No external memory required (no frame buffer)

No external clock required (uses video clk & PLLs)

No processor required (no configuration required)

Design fits in 50% of an EP3C5

Plenty of room left for Nios II processor, touchscreen driver, MP3 audio, etc.

Easy LCD Upgrade Path

No need to upgrade LCD driver (or ASSP/ASIC)

No need to re-write LCD driver software

No need to render larger frame buffers

No additional CPU cycles needed

Can adapt to different LCD sizes

System Requirements

This design was constrained and compile for 9.0 SP2.

Files

1536 FFT VHDL 9 0SP2.zip

Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 02:56 PM
Updated by:
 
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