Altera provides lots of Application Notes (AN) designed to show design engineers how to do certain functions. However, those ANs that include an FPGA design are most commonly delivered in Verilog, and rarely in VHDL. This may be a challenge for you if you are using a single language ModelSim Altera Edition for your design simulation. If your supported HDL language doesn’t match the language used in the AN, you will have to do a conversion.
The HDL conversion efforts can be especially challenging when complex MegaCore functions with simulation models are used in the design. Additionally, DSP related ANs will often use File I/O in the top level Testbench in order to stimulate/verify the HDL design with Matlab. Converting File I/O operations from Verilog to VHDL (and vice versa) can be very confusing because there are lots of ways to do this that all give different results (binary/ascii files, formatting, etc).
In this application example, I’ve converted the existing Application Note for a 1536-point FFT for 3GPP LTE radio design (AN480) from Verilog to VHDL. 3GPP is getting more attention recently by wireless and military customers. The current AN480 is written entirely in Verilog and uses Matlab to generate input data files and do bit-for-bit verification of output files written by a Verilog Testbench. I’ve created a functionally equivalent pure VHDL version of the design, including the File I/O and Matlab interaction. I’ve kept the design structure the same as much as possible, including process/module structure, signal and port names, etc. The Quartus II project now has two revisions, one for Verilog and one for VHDL. In addition, the Verilog and VHDL source directories have been kept separate to allow you to easily compare/contrast the two implementations, and choose the one that best matches your existing tool flow.
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