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1G/2.5G Ethernet Design Example for Arria V Devices

1G/2.5G Ethernet Design Example for Arria V Devices


Last Major Update 

November 27, 2015 

Introduction

This design example demonstrates 1G/2.5G Ethernet IP solution for Arria V® device family using Altera® Low Latency Ethernet 10G MAC (1G/2.5G mode) and 1G/2.5G/10G Multi-rate Ethernet PHY IP cores on Arria V GT FPGA Development Board with small form factor pluggable plus (SFP+). 

Software and Hardware Requirements

Altera uses the following software and hardware to test the design examples:

■ Quartus Prime 15.1

■ ModelSim-SE 10.3d

■ Arria V GT FPGA Development Board (5AGTFD7K3F40I3)

Design Examples components

6/6a/F1.1.png


Clocking and reset scheme

4/41/F4.1.png

b/b6/F5.1.png


There is an active high asynchronous global reset signal at design example top level (alt_mge_rd). Internal reset signals will be synchronized to respective clock domain internally, and generated by Transceiver Reset Controller.

Interface signals

Clock and Reset Signals

b/bd/T3.1.png


Ethernet MAC

4/48/T3.2.1.png


Ethernet PHY

d/df/T3.2.2.png


1G/2.5G Ethernet Reconfiguration

b/b5/T3.2.3.png


Avalon-ST Interface Signals

9/93/T3.3.png


PHY Interface Signals

b/b5/T3.4.png

Register Map

An address decoder module is provided in the design example which is instantiated in simulation testbench and hardware testing Quartus II project for demonstration purpose.

Address Offset of design example


8/84/T6.1.png

Register Offset of 1G/2.5G Ethernet Reconfiguration Controller

2/20/T6.2.png


Bit Offset of Control Register

2/2e/T6.3.png


Bit Offset of Status Register


f/ff/T6.4.png

1G/2.5G Ethernet MAC

For register map and detail explanation of the register usage, refer to Low Latency Ethernet 10G MAC User Guide, in section 4, under “Configuration Registers”.


PHY

For register map and detail explanation of the register usage, refer to Altera Transceiver PHY IP Core User Guide, in 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section, under “Configuration Registers”. 

Reconfigure PHY Speed

By default, the 1G/2.5G PHY is operating in 2.5GbE mode. In order to switch the transceiver operating speed from 2.5GbE to 1GbE or vice versa, user need to perform following steps to instruct 1G/2.5G Ethernet Reconfiguration Controller to reconfigure the PHY.

1. Read from status register to ensure reconfig_busy bit is 0.

2. Write to logical_channel_number register to select the channel to be reconfigured.

3. Write the selected operating speed to speed_select and 1 to reconfig_start bit of control register.

4. The reconfig_busy bit of status register will be read as 1 during reconfiguration process.

5. Then reconfiguration process is completed when the reconfig_busy bit is read as 0.

6. Transceiver reset sequence will be triggered automatically when the reconfiguration is completed.

Testbench

Testbench is included in the design example package for simulation verification. It operates in loopback mode.

1/1a/F8.1.png

The testbench comprise the following modules:

• Device under test (DUT)—the design example.

• Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit and the receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-MM interfaces of the design example components.

• Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the simulator console.


Testbench Files

5/54/T8.1.png


Test Scenario:

1. Design start up with channel configured to 2.5G Ethernet mode.

2. Do basic MAC configuration and PHY speed configuration for all 2 channels.

3. Wait for channel_tx_ready and channel_rx_ready signals to be asserted for all 2 channels.

4. Send 3 different type of packets:

a. 64-byte packet

b. 1518-byte packet

c. 100-byte packet

5. Repeat step 2 to 4 for 1G Ethernet mode.

Procedures to simulate the design with ModelSim-SE software

Simulation script uses QUARTUS_ROOTDIR environment variable to access Altera’s simulation model libraries. QUARTUS_ROOTDIR should has been set and pointed to the Quartus II installation path after proper installation. You need to set it manually if this environment variable is missing. Below are the steps to run the simulation:

1. Download and restore the design example: alt_mge_rd_av.zip

2. Launch Modelsim-SE 10.3d and change the directory to <project directory>/testbench/mentor/ 

3. In the TCL console window, type the below command:

do tb_run.tcl

4. After the simulation stop, Modelsim simulator will generate statistics of transmitted packets and received packets in the Transcript window. For each operating speed, if all the total 3 packets have been received successfully to channel 0 Avalon-ST RX interface, the transcript will print out “Simulation PASSED”.


Procedures to run the hardware design

The design example package comes with pre-generated RTL files that implement a two Ethernet channels. One of the channels uses the on-board SFP+ Module (J10) and the other one uses on-board SMA Connector (J20 & J21) . Below are the steps to perform hardware test:

1. Download and restore the design example: (refer to the project link above).

2. Launch the Quartus Prime 15.1 software and then open the project file, “alt_mge_top.qpf”.

3. Run full compilation for the design example. A “.sof” file will be generated once the compilation is complete.

4. Configure the Arria V FPGA (U16) on Arria V GT Development Board using the generated, “alt_mge_top.sof” file.

Note:This design example is using the default 125MHz clock source from the on-board programmable oscillator, so user is not required to use the Clock Control tool for clock frequency configuration.

5. Press User Push Button S7 to reset the system.

Note: System must be hard reset after configuration done.

6. On Quartus II Tools menu, click on System Debugging Tools and then launch System Console.

7. In the System Console command shell, change the directory to “alt_mge_rd_av/system_console”.

8. Run the command source main.tcl to initialize the reference design command list.

9. Perform the following test by running the command in the System Console command shell:

a. SFP+ loopback 

Command: TEST_EXT_LB {channel speed burst_size}

Example: TEST_EXT_LB 0 1G 1000

b. Avalon-ST loopback (The external Ethernet tester sends and receives packets thru the on-board SMA connectors)

Command: TEST_ST_LB {channel speed}

Example: TEST_ST_LB 0 1G

Version history
Revision #:
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Last update:
‎06-26-2019 02:58 PM
Updated by:
 
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