March 21, 2014
This reference design demonstrates the operation of Altera 40G base-KR4 Ethernet MAC and PHY IP solution (PDF) on a Stratix V device (5SGTMC7K2F40C2). It is configured to demonstrate on a Signal Integrity Development Kit, Stratix V GT Edition Board using Altera development tool Quartus II release 13.1. This design provides a flexible test and demonstration platform which effectively control, test, and monitor 40Gbps Ethernet packets.
• Auto-Negotation (AN) as defined in Clause 63 (only negotiation to 40GBASE-KR4 mode is supported.
• The 40GBASE-KR4 PMD as defined in Clause 84 which includes Link Training (LT) as defined in Clause 72.
• Forward Error Correction (FEC) as defined in Clause 74.
• System Console based (GUI control and status interface) flexible, reusable, and extendable user control interface allows users to dynamically configure and monitor any configuration registers provided by this demo design
The hardware platform consists of three sub-systems:
• The 40GBase-KR4 MAC and PHY IP
• Packet Client with random packet Generator and Monitor
•System Console for configuration and control of the system
This system can be represented by the following diagram :
The Altera 40G Ethernet MAC and PHY IP core is implemented in compliance with the IEEE 802.3ba 2010 Higher Speed Ethernet Standard. It is including Auto-Negotiation (AN), Link Training (LT) and Forward Error Correction (FEC). This module handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 40GbE Ethernet PCS and PMA (PHY). In the TX direction, the MAC accepts client frames, inserts inter-packet gap (IPG), preamble, start of frame delimiter (SFD), header, padding, and checksum before passing them to the PHY. The PHY encodes the MAC frame as required for reliable transmission over the media to the remote end. Similarly, in the RX direction, the MAC accepts frames from the PHY, performs checks, updates statistics counters, strips out the CRC, preamble, and SFD, and passes the rest of the frame to the client.
The Packet Client includes a Packet Generator and a Packet Monitor. These modules have 256-bit Avalon-ST interface for the data-path and connect to the 40G Ethernet MAC. There is also a 32-bit Avalon-MM configuration and status interface associated with both the generator and monitor. The generator can generate random packets. Monitor parses all packets received from MAC and checks the integrity of the packets.
This reference design provides a windows terminal program sterm.exe which can run on a PC (windows based operating system). User must provide byte addresses in order to access registers on chip using this interface.
As mentioned in previous sections, the 40G Ethernet sub-system consists of 40G MAC and PHY sub-modules. The MAC client side data path interface has two options: Avalon ST interface and Custom ST interface. This reference design uses an Avalon-ST interface which includes interface adapter. This adapter then provides a standard Avalon-ST interface for the MAC client. The MAC connects to the PHY core over XLGMII interface. The 40G Ethernet IP core can be demonstrated as the following simplified diagram:
The additional details of the IP core can be found in the User guide. The IP core evaluation package and the user guide can be downloaded from Altera website:http://www.altera.com/products/ip/iup/ethernet/m-alt-40-100gb-ethernet.html
The reference design setup essentially consists of software and hardward.
The relevant setups for each of these components are provided in detail as shown below:
The Signal Integrity Stratix V GT development board requires minimum hardware setup. Switch 6 (SW6), all 4 pin need to set to logic 0 (close). See below.
Open Integrity Stratix V GT development kit – Stratix V GX Edition v11.1.2 from Window “Start” manual “All Program” -> “Altera” -> “Transceiver Signal Integrity Development Kit – Stratix V GX Edition v11.1.2” -> “Clock Control”
Program Y3 clock frequency to 644.5313MHz.
1. Open the project file alt_e40_avalon_top_sv_kr4.qpf file in alt_e40_avalon_top_sv_kr4_13_1 directory.
2. Re-compiled the alt_e40_avalon_top_sv_kr4_13_1 project to generate .sof file.
3. Open the SignalTap II Logic Analyzer by double clicking on “Tool” -> “SignalTap II Logic Analyzer”.
4. Download the alt_e40_avalon_top_sv.sof to development board.
Open System Console at “tool” -> “System Console” -> “System Console”.
Run the Tcl script in the Tcl console: Type the following command in the Tcl script console to bring the GUI control and status penal.
1. cd system_console //Go to system_console directory
2. source main_run.tcl //Execute the scripts
After sourcing the Tcl file, there are four status and control panel will pops up. System Monitor, System Control, Packet Monitor and KR4 Status panels.
The following capture is the Tx to Rx 24cm PCB loopback test status.
The “KR4 Setting” button is an extension of KR4 PHY setting panel control. See picture below.
The example capture is a Tx to RX loopback test setting.
1. Auto negotiation function must turn off for TX to RX loopback test.
2. Force negotiated to FEC mode.
3. Reset SEQ is the reset of initiate auto negotiate and link training function.
The KR4 status control panel needs to config first before the device able the do auto negotiation and link training process. Register 0xB0, 0xC0 and 0xD0 need to set as the example above.
Bit[22:20]: 011 = rx_ctle_mode set to “Fine-gained turning at being of LT”.
Bit : 1 = Search upper VOD set.
Bit[26:24]: 010 = Rx_ctle_mode set to “Trigger DFE at end of LT”.
Bit : 0 = Disable the KR4 AN function.
Bit : 1 = Force Negotiate to FEC mode set.
Bit[6:4] : 000 = no force.
Bit : 1 = Force Negotiate to FEC mode.
Note: All change will effect only after “Reset SEQ” bit is setted.
Note: For normal two device setup, register 0xB0 and 0xC0 don’t need to change. Only register 0xD0 needs to change to 0x82b85111 for long backplane.
The system monitor panel contains all the error message and status information. The example of the capture below is one of the error free conditions. The system monitor panel will not refresh automatically. It needs to manually click on the “Update” button to refresh status.
Note: Check the system monitor panel first before generate traffic. The capture above is a example of error free conditioin.
There are three major functions in the system control panel, Soft Reset, Serial/parallel loopback, and PRBs testing funcion. The current test don't need to use those functions. See capture below.
This hardware demo design only able to generate randomize size packet. Continually generate packet can be trigger by press “Send Pkt” button. “Stop Pkt” button is stopped the traffic generation.
The packet monitor has TX/RX packet count, Error packet count and TX and RX packet count difference. See example capture below.
Note: For this TX to RX loopback test, checking the TX packet count and RX packet count is one of the methods to confirm the test pass or fail. If all TX counter are equal to RX counter, that means pass.
Click on Autorun Analysis to acquire waveform on the data tab. You can verify the status of various signals from the MegaCore function user guide.
Please follow the following steps to recompile the design.
1. Start Quartus 13.1 software. Please do not create any project.
2. Open the alt_e40_avalon_top_sv_kr4 .qpf file provided with the design.
3. Upon a successful load, start comprehensive compile and wait for the process to finish.
4. At the end of the compile, SOF file is generated.
Please note that the system flexible testing platform. We have done a limited number of testing with an intention to demonstrate the inter-op of the two sub-systems. Additional test cases can be created by creating various kind of difference setting to the sub-system.