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A10 RLDRAM3 Simulation with Micron Model

A10 RLDRAM3 Simulation with Micron Model

Design Specifications

Quartus II v15.1

ModelSim SE-64 10.0

Micron RLDRAM3 Verilog Model MT44K32M36-125

Design Overview

For Arria10 EMIF, the generated simulation example design is running the simulation test with Altera generic memory model: (Altera model.png click here to view)

This wiki link demonstrates how to replace Micron RLDRAM3 Memory Model into Arria10 RLDRAM3 generated simulation example design: (Micron model.png click here to view)

Running the Simulation

1) Open rld3.qsys file and generate the example design.

2) Copy all Micron RLDRAM3 model files from modelsend folder into ..\sim\mentor folder.

3) Open msim_setup.tcl with text editor and add the command as below into "# Compile the design files in correct order" section

eval vlog +define+x36 +define+sg125 -novopt -sv tb.v

4) Open ed_sim.v under ..\sim\sim and replace the memory module from

ed_sim_altera_emif_mem_model_151_<unique_ID> mem (

.mem_ck (emif_0_example_design_mem_mem_ck), // mem.mem_ck

.mem_ck_n (emif_0_example_design_mem_mem_ck_n), // .mem_ck_n

.mem_a (emif_0_example_design_mem_mem_a), // .mem_a

.mem_ba (emif_0_example_design_mem_mem_ba), // .mem_ba

.mem_cs_n (emif_0_example_design_mem_mem_cs_n), // .mem_cs_n

.mem_reset_n (emif_0_example_design_mem_mem_reset_n), // .mem_reset_n

.mem_we_n (emif_0_example_design_mem_mem_we_n), // .mem_we_n

.mem_ref_n (emif_0_example_design_mem_mem_ref_n), // .mem_ref_n

.mem_qk (mem_mem_mem_qk), // .mem_qk

.mem_qk_n (mem_mem_mem_qk_n), // .mem_qk_n

.mem_dk (emif_0_example_design_mem_mem_dk), // .mem_dk

.mem_dk_n (emif_0_example_design_mem_mem_dk_n), // .mem_dk_n

.mem_dq (emif_0_example_design_mem_mem_dq), // .mem_dq

.mem_dm (emif_0_example_design_mem_mem_dm) // .mem_dm



model_rldram3 mem (

.CK ({2{emif_0_example_design_mem_mem_ck}}), // mem.mem_ck

.ADDR (emif_0_example_design_mem_mem_a), // .mem_a

.BA (emif_0_example_design_mem_mem_ba), // .mem_ba

.CS_Model_ (emif_0_example_design_mem_mem_cs_n), // .mem_cs_n

.RESET (emif_0_example_design_mem_mem_reset_n), // .mem_reset_n

.WE_ (emif_0_example_design_mem_mem_we_n), // .mem_we_n

.REF_ (emif_0_example_design_mem_mem_ref_n), // .mem_ref_n

.QK_Model (mem_mem_mem_qk), // .mem_qk

.QK_Model_ (mem_mem_mem_qk_n), // .mem_qk_n

.DK (emif_0_example_design_mem_mem_dk), // .mem_dk

.DK_ (emif_0_example_design_mem_mem_dk_n), // .mem_dk_n

.DQ_Model (emif_0_example_design_mem_mem_dq), // .mem_dq

.DM (emif_0_example_design_mem_mem_dm) // .mem_dm


5) Launch ModelSim_SE and change directory into ..\sim\mentor

6) Type do

7) Observe simulation results. local_cal_success and sim_checker_traffic_gen_pass signal will get asserted.

(Micron RLDRAM Simulation.PNG

click here to view)


Version history
Last update:
‎06-21-2019 05:12 PM
Updated by: