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ALTCHIP ID in Quartus 13.1 ( Stratix V GX)

ALTCHIP ID in Quartus 13.1 ( Stratix V GX)

Overview

This design example is created to guide user on using ALTCHIP_ID IP to read out the 64-bit unique ID of the FPGA using Signal Tap. This IP started to be introduced in V series device families.

Description

The Altera Unique Chip ID (ALTCHIP_ID) IP core allows you to uniquely identify the target FPGA before device programming. This protects your device from receiving unauthorized programming data. Use the IP Catalog and parameter editor to customize and generate the ALTCHIP_ID IP core. The chip ID block has a 64 bit unique ID per die. The unique chip ID is read out from a 90 bit circular shift register by a three pin serial interface. The initial 64 bits contain the unique ID value. The last 26 bits are a concatenation of various fuse bits set during the manufacturing flow; these bits have Altera reserved values. The UniqueChip ID registerisimplemented as a barrelshiftregister.

The Altera Unique Chip ID (ALTCHIP_ID) IP core allows you to uniquely identify the target FPGA before device programming. This protects your device from receiving unauthorized programming data. Use the IP Catalog and parameter editor to customize and generate the ALTCHIP_ID IP core. The chip ID block has a 64 bit unique ID per die. The unique chip ID is read out from a 90 bit circular shift register by a three pin serial interface. The initial 64 bits contain the unique ID value. The last 26 bits are a concatenation of various fuse bits set during the manufacturing flow; these bits have Altera reserved values. The UniqueChip ID registerisimplemented as a barrelshiftregister.

Instructions

Running the design to read unique chip ID

1. Download the attached s5gx_ALTCHIP_ID131.qar file and launch the project from Quartus 13.1.

2. The design was originally tested with S5GXEA7K40 devices, thus please change the device name accordingly.

3. Compile the design. You will need the sof file to run the Signal Tap and read the ID.

4. Once the compilation successful, launch Signal Tap from tools menu.

5. All the Signal Tap options had been set. You just need to make sure that the USB-Blaster cable is detected correctly as the hardware. Click “Scan Chain” button to scan your device on-board.

6. Browse for the compiled sof file. Click on “Program device” button.

7. Once the device programmed, click on the “Autorun Analysis” button and you will see the 64-bit device unique ID is being read on chip_id signal in the Data tab.

Requirement

This design is created in Quartus 13.1. You can reinstantiate the IP when using newer Quartus II version.

 

Version history
Revision #:
2 of 2
Last update:
‎10-30-2020 02:49 PM
Updated by: