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ALTDQ DQS2 Design Example for Stratix V

ALTDQ DQS2 Design Example for Stratix V

The main objective of this document is to further assist ALTDQ_DQS2 users, especially when attempting to design and debug with this Megafunction. An example design (with simulation testbench and SDC file) targeting Stratix V, accompanied by a self-help document has been made available.

This document comprises of 3 sections:

1. Step-by-step instructions for creating a design using ALTDQ_DQS2 for Stratix V device, as well as necessary QII settings (through Assignment Editor, Pin Planner, Nativelink setup, etc.)

2. Understanding RTL Simulation Results section which may help users in RTL debugging while analyzing the signals

3. SDC Brief Walkthrough which helps elaborate the SDC constraints used in the example design.

Users are strongly encouraged to use this document together with the existing ALTDQ_DQS2 User Guide to enhance further understanding and knowledge in this topic.

Link to example design:

Link to self-help document: Altdqdqs2_Simulation_and_SDC_SV_v151.pdf

Version history
Last update:
‎06-21-2019 06:01 PM
Updated by: