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Accessing Calibration Data for UniPHY-based External Memory

Accessing Calibration Data for UniPHY-based External Memory Interface with Core Logic



Download Example Project

Design example targeting Arria V GX Transceiver Starter Board 

http://www.alterawiki.com/wiki/File:Ddr3_demo_example.qar


Overview

This example design demonstrates how to read the calibration data for UniPHY based external memory interface using debug port. The following changes are made on the EMIF example design in order to read the calibration data with core logic:

  1. A simple state machine(EXAMPLE_FSM) connects to the debug port. It is used to read calibration data through the Avalon-MM interface.
  • Refer to Example_FSM.v for the Verilog code.
  1. In-System Source & Probe (ISSP) is used to control the user design
  • Source [0] connects to global_reset_n(active low).
    • Source [1] connects to soft_reset_n(active low).
    • Source [2] connects to reset port of EXAMPLE_FSM (active high).


Running Example Design

  1. Unarchive the ddr3_demo_example.qar file.
  • This qar was created with Quartus II version 15.0.2
  1. Configure the device on the Arria V GX Transceiver Starter Board the with the sof in the project folder.
  2. Set the ISSP to source[2:0] =3’b111 to release the memory interface from reset and put the EXAMPLE_FSM in reset state.
  3. Open the EMIF_debug.stp file and trigger at the rising edge of seq_debug_rdata_valid.Click “Autorun Analysis” button to run the SignalTap II instance.


7/73/STP_trigger.png


Setting Trigger Condition

  1. Set ISSP to source[2:0]=3’b011 to release the EXAMPLE_FSM from reset(to read the calibration data).
  2. Compare the SignalTap II result with the calibration result reported by EMIF debug toolkit
  • Refer to the core_debug.h in the software folder for the memory mapped address for each of the member in debug_data_struc for this example design.
  • The memory mapped address may change if you regenerate the EMIF IP!

7/77/STP_result.png


2/25/Calibration_Report.PNG

  • SignalTap II Result

  1. Calibration Report for Example Design




Determining Memory Mapped Address

  1. Get the SEQ_CORE_DEBUG_BASE from core_debug_defines.h . This is the address for the first member in debug_data_struc.
  2. Calculate the offset based on the data size of the member and the sequence it is listed in the debug_data_struct
  • core_debug.h and core_debug_defines.h files will be created in the software folder if you enable the debug port option when generating the IP.Refer to these files in the example design to see how the memory mapped address is calculated.

b/bb/Header_files.png

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Last update:
‎06-21-2019 06:28 PM
Updated by:
 
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