This example design demonstrates how to read the calibration data for UniPHY based external memory interface using debug port. The following changes are made on the EMIF example design in order to read the calibration data with core logic:
A simple state machine(EXAMPLE_FSM) connects to the debug port. It is used to read calibration data through the Avalon-MM interface.
Refer to Example_FSM.v for the Verilog code.
In-System Source & Probe (ISSP) is used to control the user design
Source  connects to global_reset_n(active low).
Source  connects to soft_reset_n(active low).
Source  connects to reset port of EXAMPLE_FSM (active high).
Running Example Design
Unarchive the ddr3_demo_example.qar file.
This qar was created with Quartus II version 15.0.2
Configure the device on the Arria V GX Transceiver Starter Board the with the sof in the project folder.
Set the ISSP to source[2:0] =3’b111 to release the memory interface from reset and put the EXAMPLE_FSM in reset state.
Open the EMIF_debug.stp file and trigger at the rising edge of seq_debug_rdata_valid.Click “Autorun Analysis” button to run the SignalTap II instance.
Get the SEQ_CORE_DEBUG_BASE from core_debug_defines.h . This is the address for the first member in debug_data_struc.
Calculate the offset based on the data size of the member and the sequence it is listed in the debug_data_struct
core_debug.h and core_debug_defines.h files will be created in the software folder if you enable the debug port option when generating the IP.Refer to these files in the example design to see how the memory mapped address is calculated.