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This wiki page is dedicated to users that want examples that illustrate how to fix recovery timing violations related to asynchronous resets. The designs in this article have a reset circuit that goes into reset asynchronously and exits reset synchronously. As FPGA designs get larger, reset fanout is becoming more of an issue for timing closure.
This article goes hand in hand with instructional videos located here.
Addressing Reset Recovery Timing Violations in Large FPGAs Part 1
Addressing Reset Recovery Timing Violations in Large FPGAs Part 2
Three design examples are available using Quartus Prime Pro version 18.1.
Timing_Closure_Reset_Recovery_A10Small_MC - See attached at the bottom of this article
Keep in mind that all steps below may not be needed. In some cases, just one of the below may help alleviate reset recovery violations while in others all may be needed. The steps below represent a number of different ideas to help close timing on reset structures in design.
NOTE*: The hold side constraint was fixed on 5/2/19.
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