This wiki page is dedicated to users that want examples that illustrate how to fix recovery timing violations related to asynchronous resets. The designs in this article have a reset circuit that goes into reset asynchronously and exits reset synchronously. As FPGA designs get larger, reset fanout is becoming more of an issue for timing closure.
This article goes hand in hand with instructional videos located here.
Three design examples are available using Quartus Prime Pro version 18.1.
This example uses a large Arria 10 FPGA.
Timing Closure Reset Recovery A10 115Large.qar - See attached at the bottom of this article
This example uses a small Arria 10 with a falling edge final fanout stage reset register. It also uses a multi-cycle path from the falling edge reset to the reset input on the destination registers.
Timing_Closure_Reset_Recovery_A10Small_MC - See attached at the bottom of this article
This example uses a large Stratix 10 with a falling edge final fanout stage reset register. It also uses a multi-cycle path from the falling edge reset to the reset input on the destination registers.
Timing_Closure_Reset_Recovery_S10Large.qar - See attached at the bottom of this article
NOTE: Please do not use the multi-cycles used in this design until further notice. The hold side is not correct.
Steps listed in part 2 of the instructional video
Keep in mind that all steps below may not be needed. In some cases, just one of the below may help alleviate reset recovery violations while in others all may be needed. The steps below represent a number of different ideas to help close timing on reset structures in design.
Initial design reset circuit
Fanout the reset to multiple blocks. Manual split up of reset loading.
Adding an additional reset pipeline stage to better span the FPGA
Manual reset circuit replication
High-level view of single reset with large fanout into blue, BlockX, clouds
High-level view of the pipelining reset
High-level view of reset circuit replication
High-level view of additional reset circuit replication to bring reset circuit closer to destination elements
High-level view of additional fanout and pipeline stages placed in the top and top right clouds of logic
Reset circuit with falling edge clock final stage reset register. Multicycle path SDC shown.
NOTE*: The hold side constraint was fixed on 5/2/19.