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Addressing Reset Recovery Violations

Addressing Reset Recovery Violations

Description

This wiki page is dedicated to users that want examples that illustrate how to fix recovery timing violations related to asynchronous resets. The designs in this article have a reset circuit that goes into reset asynchronously and exits reset synchronously. As FPGA designs get larger, reset fanout is becoming more of an issue for timing closure.

 

This article goes hand in hand with instructional videos located here.

Addressing Reset Recovery Timing Violations in Large FPGAs Part 1

Addressing Reset Recovery Timing Violations in Large FPGAs Part 2

Examples

Three design examples are available using Quartus Prime Pro version 18.1.

 

  1. This example uses a large Arria 10 FPGA.
    • Timing Closure Reset Recovery A10 115Large.qar - See attached
  2. This example uses a small Arria 10 with a falling edge final fanout stage reset register. It also uses a multi-cycle path from the falling edge reset to the reset input on the destination registers.
    • Timing_Closure_Reset_Recovery_A10Small_MC - See attached

  3. This example uses a large Stratix 10 with a falling edge final fanout stage reset register. It also uses a multi-cycle path from the falling edge reset to the reset input on the destination registers.
    • Timing_Closure_Reset_Recovery_S10Large.qar - See attached
  • NOTE: Please do not use the multi-cycles used in this design until further notice. The hold side is not correct.

Steps listed in part 2 of the instructional video

Keep in mind that all steps below may not be needed. In some cases, just one of the below may help alleviate reset recovery violations while in others all may be needed. The steps below represent a number of different ideas to help close timing on reset structures in design.

* Initial design reset circuit

800px-Reset_Circuit.JPG

0/02/Reset_Circuit.JPG

* Fanout the reset to multiple blocks. Manual split up of reset loading.

800px-Reset_Fanout_Stage1.JPG

7/7a/Reset_Fanout_Stage1.JPG

*Adding an additional reset pipeline stage to better span the FPGA 

800px-Reset_Fanout_Stage2.JPG

f/f6/Reset_Fanout_Stage2.JPG

* Manual reset circuit replication

800px-Reset_Replication.JPG

c/cc/Reset_Replication.JPG

* High-level view of single reset with large fanout into blue, BlockX, clouds

 

800px-High_level_reset_view1.JPG

6/6b/High_level_reset_view1.JPG 

* High-level view of the pipelining reset

800px-High_level_reset_view2.JPG

b/b5/High_level_reset_view2.JPG

* High-level view of reset circuit replication

800px-High_level_reset_view3.JPG

0/0f/High_level_reset_view3.JPG

 

* High-level view of additional reset circuit replication to bring reset circuit closer to destination elements

800px-High_level_reset_view4.JPG

3/38/High_level_reset_view4.JPG

* High-level view of additional fanout and pipeline stages placed in the top and top right clouds of logic

800px-High_level_reset_view5.JPG

 a/ac/High_level_reset_view5.JPG

* Reset circuit with falling edge clock final stage reset register. Multicycle path SDC shown.

800px-Reset_Circuit_MultiCycle.JPG

c/cd/Reset_Circuit_MultiCycle.JPG

NOTE*: The hold side constraint was fixed on 5/2/19.

 

Attachments
Version history
Revision #:
4 of 4
Last update:
‎06-26-2020 10:08 AM
Updated by: