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Altera 8B10B MegaCore to Altera Cookbook 8B10B Migration Guidelines

Altera 8B10B MegaCore to Altera Cookbook 8B10B Migration Guidelines



Device Support

Altera 8B10B Mega Core is already End of Life and does not support newer Altera devices such as Arria 10, Stratix V, Arria V, and Cyclone V.

Altera Cookbook 8B10B Encoder and Decoder use Stratix II LCELL components. But, you can modify the RTL code to fit them to your target device. Replace stratixii_lcell_comb in the RTL with:

stratixiv_lcell_comb for Stratix IV devices

arriaii_lcell_comb for Arria II devices

cycloneiv_lcell_comb for Cyclone IV devices

stratixv_lcell_comb for Stratix V devices

arriav_lcell_comb for Arria V devices

cyclonev_lcell_comb for Cyclone V devices

twentynm_lcell_comb for Arria 10 devices

Fmax

The Fmax should be high enough. Quartus Prime software version 16.0 reported the Fmax of these 8B10B Encoder and Decoder for Stratix IV C2 core speed grade as below.

Altera 8B10B Encoder with ‘Register Input/Output’: 465.33 MHz

Altera 8B10B Decoder: 800 MHz

Altera Cookbook 8B10B Encoder: 690.61 MHz

Altera Cookbook 8B10B Decoder: 681.66 MHz

Latency

Altera Cookbook Encoder latency is same as the Altera 8B10B Encoder without ‘Register Input/Outputs’ option. If you want the same latency as the Altera 8B10B Encoder with ‘Register Input/Outputs’, additional Flip-Flop needs to be added.

Altera Cookbook Decoder latency is one clock cycle shorter than the Altera 8B10B Decoder latency. If you want the same latency as the Altera 8B10B Decoder, additional Flip-Flop needs to be added.

Altera 8B10B Encoder without ‘Register Input/Output’: 2 clock latency

Altera 8B10B Encoder with ‘Register Input/Output’: 3 clock latency

Altera 8B10B Decoder: 2 clock latency

Altera Cookbook 8B10B Encoder: 2 clock latency

Altera Cookbook 8B10B Decoder: 1 clock latency

Functions

The Cookbook 8B10B Encoder does not have the kerr output function unlike Altera 8B10B MegaCore.

The Cookbook 8B10B Decoder does not have the idle_del function unlike Altera 8B10B MegaCore.

Both decoders output invalid data for the first three clock cycles after the reset deassertion due to the internal latency. You will see mismatch between the MegaCore and the Cookbook during the first three clock cycles, but they should be ignored.

Port Mapping

Port names of the Altera Cookbook 8B10B Encoder and Decoder are different from the Altera 8B10B MegaCore. If you want to have same port name, convert signal names as below.

Encoder (Download wrapper file File:Encoder 8b10b wrapper.v)

assign rst = ~reset_n ;

assign kin_ena = kin ;

assign ein_ena = ena ;

assign ein_dat = datain ;

assign ein_rd = (rdforce)? rdin: eout_rdreg ;


assign dataout = eout_dat ;

assign valid = eout_val ;

assign rdout = eout_rdreg ;

assign rdcascade = eout_rdcomb ;

Decoder (Download wrapper file File:Decoder 8b10b wrapper.v

assign rst = ~reset_n ;

assign din_ena = ena ;

assign din_dat = datain ;

assign din_rd = (rdforce)? rdin: dout_rdreg ;


assign valid = dout_val ;

assign dataout = dout_data ;

assign dout_k = kout ;

assign kerr = dout_kerr ;

assign rdcascade = dout_rdcomb ;

assign rdout = dout_rdreg ;

assign rderr = dout_rderr ;

Stratix IV Testbench

This testbench has Altera 8B10B Encoder and Decoder and Altera Cookbook 8B10B Encoder and Decoder. The latency for the Encoders and Decoders are three and two respectively. 


9/90/8b10b_testbench.PNG


External Links

Advanced Synthesis Cookbook - Altera

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Last update:
‎06-21-2019 06:42 PM
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