Altera EMIF (External memory interface) Resources and Pin Planning (AERP) tool is a tool used to estimate EMIF design resouce utilization and perform pin planning without the need to create a design. This tool helps in estimating the number of I/O pins, DQ/DQS group, PLLs, DLLs, OCTs and clock networks utilized in a EMIF design. At the same, this tool also provides pin connection guidelines and read data group assignment.
To use this tool, you have to install two softwares below into your machine:
Open the user guide and follow the guidelines in the user guide
The estimated resources uutilization is based on Altera UniPHY IPs.
Support devices that support Altera UniPHY IPs only.
These numbers are estimation and for reference only. You should always try the proposed pinouts by creating a project in the Quartus II software with the correct I/O standard and OCT assignments before finalizing the pinouts and PCB sign-off.
LE (Logic element) estimation is not offered in this tool. You should compile your design using Quartus II to obtain the accurate LE usage.
For design targeting HMC, please use AERP tool version 2.1 with Quartus II 12.0, as the latest Quartus II version cannot extract out the HMC pin out.
Version 2.0: Support Quartus II 11.1sp2, added Arria V and Cyclone V support, Hard Memory Interface support
Version 2.1: Support Quartus II 12.0, added LPDDR2 support
Version 2.2: Support Quartus II 12.1, added Arria V GZ and RLDRAM3 support