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Altera Triple-Speed Ethernet IP Core Timing Constraints

Altera Triple-Speed Ethernet IP Core Timing Constraints



Introduction

Altera provides constraint files to ensure that the Triple-Speed Ethernet MegaCore function meets design timing requirements in Altera devices. You might need to add timing constraints which are external to the MegaCore function.


How to modify the generated constraint file?

Follow the steps below to modify the generated constraint file:



Open and modify generated constraint files


  • Edit <variation_name>_constraints.tcl and <variation_name>_constraints.sdc according to your customized design. For example, if you change the clock names at the top-level design, edit the customer modifiable constraints in the <variation_name>_constraints.sdc file to change the clock names shown below:

# Name the clocks that will be coming into the tse core named changed from top level


set TX_CLK "tx_clk"

set RX_CLK "rx_clk"

set CLK "clk"

set FF_TX_CLK "ff_tx_clk"

set FF_RX_CLK "ff_rx_clk"

set TBI_TX_CLK "tbi_tx_clk"

set TBI_RX_CLK "tbi_rx_clk"

set REF_CLK "ref_clk"



The generated SDC file includes the clock names for all core configurations. However, you only need to constrain the clocks that are relevant to your core configuration. For the clock names that require timing constraint in the SDC, refer to Table 2-2 to Table 2-6.


  • Table 2-2 lists the clock signals that require timing constraint for 10/100/1000 Mbps Ethernet MAC.
  • Table 2-3 lists the clock signals that require timing constraint for 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS.
  • Table 2-4 lists the clock signals that require timing constraint for 1000BASE-X/SGMII PCS.
  • Table 2-5 lists the clock signals that require timing constraint for 10/100Mb Small MAC and 1000Mb Small MAC.



Table 2-2 Timing Constraint Requirement for 10/100/1000 Mbps Ethernet MAC Clock Signals

Clocks

Configurations(1)

With internal FIFO

Without internal FIFO

TX_CLKYesYes
RX_CLKYesYes
CLKYesYes
FF_TX_CLKYes-
FF_RX_CLKYes-
TBI_TX_CLK--
TBI_RX_CLK--
REF_CLK --

Notes to Table 2-2:

(1) Yes indicates that the clock requires timing constraint at the top-level design.

— indicates that the clock is not applicable for the given configuration.


Table 2-3 Timing Constraint Requirement for 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS Clock Signals

Clocks

Configurations(1)

With internal FIFO

Without internal FIFO

With PMA block

Without PMA block

With PMA block

Without PMA block

TX_CLK----
RX_CLK----
CLKYesYesYesYes
FF_TX_CLKYesYes--
FF_RX_CLKYesYes--
TBI_TX_CLK-Yes-Yes
TBI_RX_CLK-Yes-Yes
REF_CLKYes-Yes-

Notes to Table 2-3:

(1) Yes indicates that the clock requires timing constraint at the top-level design.

— indicates that the clock is not applicable for the given configuration.


Table 2-4 Timing Constraint Requirement for 1000BASE-X/SGMII PCS Clock Signals

Clocks

Configurations (1)

With PMA block

Without PMA block

TX_CLK--
RX_CLK--
CLKYesYes
FF_TX_CLK--
FF_RX_CLK--
TBI_TX_CLK-Yes
TBI_TX_CLK-Yes
REF_CLKYes-

Notes to Table 2-4:

(1) Yes indicates that the clock requires timing constraint at the top-level design.

— indicates that the clock is not applicable for the given configuration.


Table 2-5 Timing Constraint Requirement for 10/100 Mbps Small MAC and 1000 Mbps Small MAC Clock Signals

Clocks

Configurations (1)

With internal FIFO

TX_CLKYes
RX_CLKYes
CLKYes
FF_TX_CLKYes
FF_RX_CLKYes
TBI_TX_CLK-
TBI_RX_CLK-
REF_CLK-

Notes to Table 2-5:

(1) Yes indicates that the clock requires timing constraint at the top-level design.

— indicates that the clock is not applicable for the given configuration.




Constrain design clock frequency


  • Constrain the clock frequency according to your customized design. If your design requires a different operating frequency, edit the SDC file to make changes to the frequency parameters shown below:

# Frequency of network-side interface clocks or reference clocks

set TSE_CLOCK_FREQUENCY "125 MHz"


# Frequency of FIFO data interface clocks

set FIFO_CLOCK_FREQUENCY "100 MHz"


# Frequency of control and status interface clock

set DEFAULT_SYSTEM_CLOCK_SPEED "66 MHz"

For the list of clock names that will be affected by these frequency parameters, refer to Table 2-6. 

Clocks

Frequency Parameter (1)

TSE_CLOCK_FREQUENCY

FIFO_CLOCK_FREQUENCY

DEFAULT_SYSTEM_CLOCK_SPEED

TX_CLK

Yes

-

-

RX_CLK

Yes

-

-

CLK

-

-

Yes

FF_TX_CLK

-

Yes

-

FF_RX_CLK

-

Yes

-

TBI_TX_CLK

Yes

-

-

TBI_RX_CLK

Yes

-

-

REF_CLK

Yes

-

-


Notes to Table 2-6:

(1) Yes indicates that the clock is applicable to the frequency parameter.

— indicates that the clock is not applicable for the frequency parameter.




To get more understanding on TSE timing design constraint and its flow, please refer to this design example: www.alterawiki.com/wiki/Altera_Triple-Speed_Ethernet_Timing_Contraints_Design_Example


For more information about timing analyzers, refer to the Timing Analysis section in volume 3 of the Quartus II Handbook and the Quartus II Help.

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