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Altera Triple-Speed Ethernet Timing Contraints Design Example (Multi-core)

Altera Triple-Speed Ethernet Timing Contraints Design Example (Multi-core)



Last Major Update 

August 13, 2012

 

Introduction 

Altera Timing Contraints Design Example for multiple Triple-Speed Ethernet (TSE) IP cores. The following two design examples demonstrate how to use the Altera MegaWizard generated SDC file to constrain timing when you have multiple Triple-Speed Ethernet (TSE) IP cores in your design.

  • Design example 1: Multiple TSE IP cores (identical core configuration) with different IP output file names.
  • Design example 2: Multiple TSE IP cores (identical core configuration) with the same IP output file name.

These design examples are only applicable when you use the same core configuration parameter settings in the MegaWizard interface for the TSE IP cores in your design. The TSE MegaCore function generates timing constraint file, <variation_name>_constraints.sdc where the variation name is the IP output file name. Therefore, you will see multiple <variation_name>_constraints.sdc files in your IP project directory when you specify different IP output file name for the TSE IP cores. To minimize the number of timing warnings related to Ignore Filter, Ignore Create Clock and Illegal clocks in the timing report, you can modify the generated SDC files according to these design examples.


Design example 1: Multiple TSE IP cores with different IP output file names

This design example instantiates two TSE IP cores with the following core configuration:

Core Variation: 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS

Use Internal FIFO: On

Use Transceiver Block: On (GXB)

Number of Ports: 1

IP output file name: TSE_0.v, TSE_1.v

Generated timing constraint files: TSE_0_constraints.sdc, TSE_1_constraints.sdc


Design Block Diagram

4/47/Altera_TSE_Timing_Contraints_Design_Example_%28Multi-core%29_block_diagram_1.jpg


Timing Constraint

Steps to Constrain Timing Using MegaWizard Generated SDC File 

1. Create a new SDC file for the top level design and add the following commands to constrain PLL input and output clocks.

  • create_clock -name {CLK_100M} -period 10.000 -waveform { 0.000 5.000 } [get_ports {CLK_100M}]
  • derive_pll_clocks

Constrain reconfig_clk (if applicable) manually to avoid unconstrained clock warning in the TimeQuest timing analyzer.


2. Open TSE_0_constraints.sdc file.


3. Set Clock Path.

(a) set CLK "CLK_50M"

(b) set REF_CLK "gxb_ref_clk"

If you are using PLL-generated output clock as the clock source, obtain the PLL clock path from the TimeQuest timing analyzer -> clocks report, and set the clock name according to the PLL output clock path.

(c) set FF_TX_CLK "altera_pll_tse_inst|altera_pll_tse_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk"

(d) set FF_RX_CLK "altera_pll_tse_inst|altera_pll_tse_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk"

To minimize ignore create clock warnings in the TimeQuest timing analyzer report, you may comment out the unused clock names.

However, you will see "Ignored filter" warning and "Ignored create_clock" warning messages for FF_TX_CLK and FF_RX_CLK during timing analysis due to the limitation of the generated SDC file. You may safely ignore these warning messages.


4. Set Clock Frequency (you may comment out frequency parameters that are not applicable to your design)

Frequency of network-side interface clocks or reference clocks.

set TSE_CLOCK_FREQUENCY "125 MHz"

# Frequency of FIFO data interface clocks.

set FIFO_CLOCK_FREQUENCY "125 MHz"

# Frequency of MAC or PCS control and status interface clock.

set DEFAULT_SYSTEM_CLOCK_SPEED "50 MHz"


5. Open TSE_1_constraints.sdc file and repeat Step 3 and Step 4.

Since the CLK and REF_CLK clock source is shared between TSE_0 and TSE_1, you will see the following warning messages during timing analysis.

  • Warning (332043): Overwriting existing clock: altera_tse_gxb_ref_clk_
  • Warning (332043): Overwriting existing clock: altera_tse_CLK_50M_


6. Repeat Step 2 to Step 4 if you re-generate the TSE IP core.

 The modified SDC file will replaced with the original SDC file during IP re-generation.


7. Check TimeQuest Timing Analyzer report for any unconstrained or illegal clocks.


Download Design Example

Download the design files used in this example:

http://www.alterawiki.com/wiki/File:TSE_multicore_SDC_DE1_Top.qar

Software: Quartus II version 12.0

Device family: Stratix V


Design example 2: Multiple TSE IP cores with the same IP output file name

This design example instantiates two TSE IP cores with the following core configuration:

Core Variation: 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS

Use Internal FIFO: On

Use Transceiver Block: On (GXB)

Number of Ports: 1

IP output file name: TSE_0.v

Generated timing constraint files: TSE_0_constraints.sdc

This design example will use the TSE_0_constraints.sdc to constrain timing for two TSE IP cores.


Design Block Diagram

4/47/Altera_TSE_Timing_Contraints_Design_Example_%28Multi-core%29_block_diagram_1.jpg


Timing Constraint

Steps to Constrain Timing Using MegaWizard Generated SDC File

1. Create a new SDC file for the top level design and add the following commands to constrain PLL input and output clocks.

create_clock -name {CLK_100M} -period 10.000 -waveform { 0.000 5.000 } [get_ports {CLK_100M}] 

derive_pll_clocks 

Constrain reconfig_clk (if applicable) manually to avoid unconstrained clock warning in the TimeQuest timing analyzer.


2. Open TSE_0_constraints.sdc file.


3. Set Clock Path.

(a) set CLK "CLK_50M"

(b) set REF_CLK "gxb_ref_clk"

If you are using PLL-generated output clock as the clock source, obtain the PLL clock path from the TimeQuest timing analyzer -> clocks report, and set the clock name according to the PLL output clock path.

(c) set FF_TX_CLK "altera_pll_tse_inst|altera_pll_tse_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk"

(d) set FF_RX_CLK "altera_pll_tse_inst|altera_pll_tse_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk"

To minimize ignore create clock warnings in the TimeQuest timing analyzer report, you may comment out the unused clock names.

However, you will see "Ignored filter" warning and "Ignored create_clock" warning messages for FF_TX_CLK and FF_RX_CLK during timing analysis due to the limitation of the generated SDC file. You may safely ignore these warning messages.


4. Set Clock Frequency (you may comment out frequency parameters that are not applicable to your design)

Frequency of network-side interface clocks or reference clocks.

set TSE_CLOCK_FREQUENCY "125 MHz"

# Frequency of FIFO data interface clocks.

set FIFO_CLOCK_FREQUENCY "125 MHz"

# Frequency of MAC or PCS control and status interface clock.

set DEFAULT_SYSTEM_CLOCK_SPEED "50 MHz"


5. Repeat Step 2 to Step 4 if you re-generate the TSE IP core.

The modified SDC file will replaced with the original SDC file during IP re-generation.


6. Check TimeQuest Timing Analyzer report for any unconstrained or illegal clocks.


Tips: If the TSE cores do not share the same clock source, you should specify different IP output file name for each TSE IP core. By doing so, each TSE IP core will have its own generated SDC file and you can use the SDC file to constrain timing for the respective TSE IP core.

 

Download Design Example

Download the design files used in this example:

http://www.alterawiki.com/wiki/File:TSE_multicore_SDC_DE2_Top.qar

Software: Quartus II version 12.0

Device family: Stratix V

Disclaimer 

© [2012] Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable, misleading or inaccurate.

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